Datasheet LTC2433-1 (Analog Devices) - 8

LTC2433-1
U U W U APPLICATIO S I FOR ATIO CONVERTER OPERATION
conversion. There is no latency in the conversion result. The data output corresponds to the conversion just per-
Converter Operation Cycle
formed. This result is shifted out on the serial data out pin The LTC2433-1 is a low power, ∆Σ ADC with differential (SDO) under the control of the serial clock (SCK). Data is input/reference and an easy-to-use 3-wire serial interface updated on the falling edge of SCK allowing the user to (see Figure 1). Its operation is made up of three states. reliably latch data on the rising edge of SCK (see Figure 3). The converter operating cycle begins with the conversion, The data output state is concluded once 19 bits are read followed by the low power sleep state and ends with the out of the ADC or when CS is brought HIGH. The device data output (see Figure 2). The 3-wire interface consists automatically initiates a new conversion and the cycle of serial data output (SDO), serial clock (SCK) and chip repeats. In order to maintain compatibility with 24-/32-bit select (CS). data transfers, it is possible to clock the LTC2433-1 with additional serial clock pulses. This results in additional Initially, the LTC2433-1 performs a conversion. Once the data bits which are logic HIGH. conversion is complete, the device enters the sleep state. The part remains in the sleep state as long as CS is HIGH. Through timing control of the CS and SCK pins, the While in this sleep state, power consumption is reduced by LTC2433-1 offers several flexible modes of operation nearly two orders of magnitude. The conversion result is (internal or external SCK and free-running conversion held indefinitely in a static shift register while the converter modes). These various modes do not require program- is in the sleep state. ming configuration registers; moreover, they do not dis- turb the cyclic operation described above. These modes of Once CS is pulled LOW, the device exits the low power operation are described in detail in the Serial Interface mode and enters the data output state. If CS is pulled HIGH Timing Modes section. before the first rising edge of SCK, the device returns to the low power sleep mode and the conversion result is still
Conversion Clock
held in the internal static shift register. If CS remains LOW A major advantage the delta-sigma converter offers over after the first rising edge of SCK, the device begins conventional type converters is an on-chip digital filter outputting the conversion result. Taking CS high at this (commonly implemented as a Sinc or Comb filter). For point will terminate the data output state and start a new high resolution, low frequency applications, this filter is typically designed to reject line frequencies of 50Hz and CONVERT 60Hz plus their harmonics. The filter rejection perfor- mance is directly related to the accuracy of the converter system clock. The LTC2433-1 incorporates a highly accu- SLEEP rate on-chip oscillator. This eliminates the need for exter- nal frequency setting components such as crystals or oscillators. Clocked by the on-chip oscillator, the FALSE CS = LOW LTC2433-1 achieves a minimum of 87dB rejection over AND SCK the range 49Hz to 61.2Hz. TRUE
Ease of Use
DATA OUTPUT 24331 F02 The LTC2433-1 data output has no latency, filter settling delay or redundant data associated with the conversion cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing
Figure 2. LTC2433-1 State Transition Diagram
multiple analog voltages is easy. 24331fa 8