Datasheet LTC2351-14 (Analog Devices) - 8

LTC2351-14
PIN FUNCTIONS VDD (Pin 25):
3V Positive Digital Supply. This pin sup- a fi xed state during conversion and during the subsequent plies 3V to the logic section. Bypass to DGND pin and conversion to read data. solid analog ground plane with a 10μF ceramic capacitor
BIP (Pin 29):
Bipolar/Unipolar Mode. The input dif- (or 10μF tantalum in parallel with 0.1μF ceramic). Keep ferential range is 0V – 2.5V when BIP is LOW, and it is in mind that internal digital output signal currents fl ow ±1.25V when BIP is HIGH. Must be kept in fi xed state through this pin. Care should be taken to place the 0.1μF during conversion and during subsequent conversion to bypass capacitor as close to Pin 25 as possible. Pin 25 read data. When changing BIP between conversions the must be tied to Pin 24. full acquisition time must be allowed before starting the
SEL2 (Pin 26):
Most Signifi cant Bit Controlling the next conversion. The output data is in 2’s complement Number of Channels Being Converted. In combination format for bipolar mode and straight binary format for with SEL1 and SEL0, 000 selects just the fi rst channel unipolar mode. (CH0) for conversion. Incrementing SELx selects addi-
CONV (Pin 30):
Convert Start. Holds the six analog input tional channels(CH0–CH5) for conversion. 101, 110 or 111 signals and starts the conversion on the rising edge. Two select all six channels for conversion. Must be kept in a CONV pulses with SCK in fi xed HIGH or fi xed LOW state fi xed state during conversion and during the subsequent starts nap mode. Four or more CONV pulses with SCK in conversion to read data. fi xed HIGH or fi xed LOW state starts sleep mode.
SEL1 (Pin 27):
Middle Signifi cant Bit Controlling the
DGND (Pin 31):
Digital Ground. This ground pin must be Number of Channels Being Converted. In combination tied directly to the solid ground plane. Digital input signal with SEL0 and SEL2, 000 selects just the fi rst channel currents fl ow through this pin. (CH0) for conversion. Incrementing SELx selects additional channels for conversion. 101, 110 or 111 select all six
SCK (Pin 32):
External Clock Input. Advances the con- channels (CH0–CH5) for conversion. Must be kept in a version process and sequences the output data at SD0 fi xed state during conversion and during the subsequent (Pin1) on the rising edge. One or more SCK pulses wake conversion to read data. from sleep or nap power saving modes. 16 clock cycles are needed for each of the channels that are activated by
SEL0 (Pin 28):
Least Signifi cant Bit Controlling the SELx (Pins 26, 27, 28), up to a total of 96 clock cycles Number of Channels Being Converted. In combination needed to convert and read out all six channels. with SEL1 and SEL2, 000 selects just the fi rst channel (CH0) for conversion. Incrementing SELx selects addi-
Exposed Pad (Pin 33):
GND. Must be tied directly to the tional channels for conversion. 101, 110 or 111 select all solid ground plane. six channels (CH0–CH5) for conversion. Must be kept in 235114fb 8