Datasheet LTC2282 (Analog Devices) - 8

LTC2282
PIN FUNCTIONS A + INA (Pin 1):
Channel A Positive Differential Analog and a ±1V input range. An external reference greater than Input. 0.5V and less than 1V applied to SENSEB selects an input range of ±V
A –
SENSEB. ±1V is the largest valid input range.
INA (Pin 2):
Channel A Negative Differential Analog Input.
VCMB (Pin 20):
Channel B 1.5V Output and Input Common Mode Bias. Bypass to ground with 2.2μF ceramic chip
REFHA (Pins 3, 4):
Channel A High Reference. Short capacitor. Do not connect to V together and bypass to Pins 5, 6 with a 0.1μF ceramic chip CMA. capacitor as close to the pin as possible. Also bypass to
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX is Pins 5, 6 with an additional 2.2μF ceramic chip capacitor high, channel A comes out on DA0-DA11, OFA; channel B and to ground with a 1μF ceramic chip capacitor. comes out on DB0-DB11, OFB. If MUX is low, the output busses are swapped and channel A comes out on DB0-
REFLA (Pins 5, 6):
Channel A Low Reference. Short DB11, OFB; channel B comes out on DA0-DA11, OFA. To together and bypass to Pins 3, 4 with a 0.1μF ceramic chip multiplex both channels onto a single output bus, connect capacitor as close to the pin as possible. Also bypass to MUX, CLKA and CLKB together. (This is not recommended Pins 3, 4 with an additional 2.2μF ceramic chip capacitor at clock frequencies above 80Msps.) and to ground with a 1μF ceramic chip capacitor.
SHDNB (Pin 22):
Channel B Shutdown Mode Selection
VDD (Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to Pin. Connecting SHDNB to GND and OEB to GND results GND with 0.1μF ceramic chip capacitors. in normal operation with the outputs enabled. Connecting
CLKA (Pin 8):
Channel A Clock Input. The input sample SHDNB to GND and OEB to VDD results in normal operation starts on the positive edge. with the outputs at high impedance. Connecting SHDNB
CLKB (Pin 9):
Channel B Clock Input. The input sample to VDD and OEB to GND results in nap mode with the starts on the positive edge. outputs at high impedance. Connecting SHDNB to VDD and OEB to VDD results in sleep mode with the outputs
REFLB (Pins 11, 12):
Channel B Low Reference. Short at high impedance. together and bypass to Pins 13, 14 with a 0.1μF ceramic chip capacitor as close to the pin as possible. Also bypass
OEB (Pin 23):
Channel B Output Enable Pin. Refer to to Pins 13, 14 with an additional 2.2μF ceramic chip capaci- SHDNB pin function. tor and to ground with a 1μF ceramic chip capacitor.
NC (Pins 24, 25, 41, 42):
Do Not Connect These Pins.
REFHB (Pins 13, 14):
Channel B High Reference. Short
DB0 – DB11 (Pins 26 to 30, 33 to 39):
Channel B Digital together and bypass to Pins 11, 12 with a 0.1μF ceramic Outputs. DB11 is the MSB. chip capacitor as close to the pin as possible. Also bypass
OGND (Pins 31, 50):
Output Driver Ground. to Pins 11, 12 with an additional 2.2μF ceramic chip capaci- tor and to ground with a 1μF ceramic chip capacitor.
OVDD (Pins 32, 49):
Positive Supply for the Output Drivers. Bypass to ground with a 0.1μF ceramic chip capacitor.
A – INB (Pin 15):
Channel B Negative Differential Analog Input.
OFB (Pin 40):
Channel B Overfl ow/Underfl ow Output. High when an overfl ow or underfl ow has occurred.
A + INB (Pin 16):
Channel B Positive Differential Analog Input.
DA0 – DA11 (Pins 43 to 48, 51 to 56):
Channel A Digital Outputs. DA11 is the MSB.
GND (Pins 17, 64):
ADC Power Ground.
OFA (Pin 57):
Channel A Overfl ow/Underfl ow Output. High
SENSEB (Pin 19):
Channel B Reference Programming Pin. when an overfl ow or underfl ow has occurred. Connecting SENSEB to VCMB selects the internal reference and a ±0.5V input range. VDD selects the internal reference
OEA (Pin 58):
Channel A Output Enable Pin. Refer to SHDNA pin function. 2282fb 8