Datasheet LTC2258-14, LTC2257-14, LTC2256-14 (Analog Devices) - 6

LTC2258-14 LTC2257-14/LTC2256-14
p ower requireMenTs The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 9) LTC2258-14 LTC2257-14 LTC2256-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS CMOS Output Modes: Full Data Rate and Double Data Rate
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.1 1.9 1.1 1.9 1.1 1.9 V IVDD Analog Supply Current DC Input l 44.7 49.5 27 30 19.5 22 mA Sine Wave Input 45.3 27.9 19.9 mA IOVDD Digital Supply Current Sine Wave Input, OVDD=1.2V 2.6 1.6 1.1 mA PDISS Power Dissipation DC Input l 80.5 90 48.6 54 35.1 40 mW Sine Wave Input, OVDD=1.2V 84.7 52.1 37.1 mW
LVDS Output Mode
VDD Analog Supply Voltage (Note 10) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V OVDD Output Supply Voltage (Note 10) l 1.7 1.9 1.7 1.9 1.7 1.9 V IVDD Analog Supply Current Sine Wave Input l 48.9 54 31.4 35 23.5 26 mA IOVDD Digital Supply Current Sine Input, 1.75mA Mode l 20.7 23 20.7 23 20.7 23 mA (0VDD = 1.8V) Sine Input, 3.5mA Mode l 40.5 44 40.5 44 40.5 44 mA PDISS Power Dissipation Sine Input, 1.75mA Mode l 125.3 139 93.8 105 79.6 89 mW Sine Input, 3.5mA Mode l 160.9 177 129.4 143 115.2 126 mW
All Output Modes
PSLEEP Sleep Mode Power 0.5 0.5 0.5 mW PNAP Nap Mode Power 9 9 9 mW PDIFFCLK Power Increase with Differential Encode Mode Enabled 10 10 10 mW (No increase for Nap or Sleep Modes)
Ti Ming characTerisTics The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC2258-14 LTC2257-14 LTC2256-14 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fS Sampling Frequency (Note 10) l 1 65 1 40 1 25 MHz tL ENC Low Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2.0 7.69 500 2.00 12.5 500 2.00 20 500 ns tH ENC High Time (Note 8) Duty Cycle Stabilizer Off l 7.3 7.69 500 11.88 12.5 500 19 20 500 ns Duty Cycle Stabilizer On l 2.0 7.69 500 2.00 12.5 500 2.00 20 500 ns tAP Sample-and-Hold 0 0 0 ns Acquisition Delay Time
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (CMOS Modes: Full Data Rate and Double Data Rate)
tD ENC to Data Delay CL = 5pF (Note 8) l 1.1 1.7 3.1 ns tC ENC to CLKOUT Delay CL = 5pF (Note 8) l 1 1.4 2.6 ns tSKEW DATA to CLKOUT Skew tD – tC (Note 8) l 0 0.3 0.6 ns Pipeline Latency Full Data Rate Mode 5.0 Cycles Double Data Rate Mode 5.5 Cycles 225814fc 6 Fo F r o rmo m r o e r e inf n o f r o m r a m t a iton o n ww w w w . w line n a e r a .co c m o / m L / T L C T 2 C 2 2 5 2 8 5 - 8 1 - 4 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts