Datasheet LTC2258-14, LTC2257-14, LTC2256-14 (Analog Devices)

LTC2258-14 LTC2257-14/LTC2256-14 14-Bit, 65/40/25Msps Ultralow Power 1.8V ADCs
FeaTures DescripTion
n 74dB SNR The LTC®2258-14/LTC2257-14/LTC2256-14 are sam- n 88dB SFDR pling 14-bit A/D converters designed for digitizing high n Low Power: 81mW/49mW/35mW frequency, wide dynamic range signals. They are perfect n Single 1.8V Supply for demanding communications applications with AC n CMOS, DDR CMOS or DDR LVDS Outputs performance that includes 74dB SNR and 88dB spurious n Selectable Input Ranges: 1VP-P to 2VP-P free dynamic range (SFDR). Ultralow jitter of 0.17psRMS n 800MHz Full-Power Bandwidth S/H allows undersampling of IF frequencies with excellent n Optional Data Output Randomizer noise performance. n Optional Clock Duty Cycle Stabilizer DC specs include ±1LSB INL (typical), ±0.3LSB DNL (typi- n Shutdown and Nap Modes cal) and no missing codes over temperature. The transition n Serial SPI Port for Configuration noise is a low 1.13LSBRMS. n Pin Compatible 14-Bit and 12-Bit Versions n 40-Pin (6mm × 6mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate
applicaTions
output power supply allows the CMOS output swing to range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single ended with a sine wave, PECL, LVDS, TTL or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multi-Channel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion LTC2258-14 2-Tone FFT, fIN = 68MHz and 69MHz
1.8V 1.2V 0 V TO 1.8V DD –10 OVDD –20 –30 + D13 14-BIT • –40 ANALOG CMOS INPUT CORRECTION OUTPUT PIPELINED • –50 INPUT OR S/H LOGIC DRIVERS ADC CORE – • LVDS –60 D0 –70 AMPLITUDE (dBFS) –80 OGND –90 CLOCK/DUTY –100 CYCLE –110 CONTROL –120 0 10 20 30 225814 TA01a GND FREQUENCY (MHz) 65MHz CLOCK 225814 TA01b 225814fc Fo F r o rmo m r o e r e inf n o f r o m r a m t a iton o n ww w w w . w line n a e r a .co c m o / m L / T L C T 2 C 2 2 5 2 8 5 - 8 1 - 4 1 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configurations Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Revision History Related Parts