Datasheet LTC2201 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 20Msps ADC |
| Seiten / Seite | 24 / 1 — FEATURES. DESCRIPTION. Sample Rate: 20Msps. 81.6dB SNR and 100dB SFDR … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
FEATURES. DESCRIPTION. Sample Rate: 20Msps. 81.6dB SNR and 100dB SFDR (2.5V Range). 90dB SFDR at 70MHz (1.667VP-P Input Range)
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LTC2201 16-Bit, 20Msps ADC
FEATURES DESCRIPTION
n
Sample Rate: 20Msps
The LTC®2201 is a 20Msps, sampling 16-bit A/D converter n
81.6dB SNR and 100dB SFDR (2.5V Range)
designed for digitizing high frequen cy, wide dynamic range n
90dB SFDR at 70MHz (1.667VP-P Input Range)
signals with input frequencies up to 380MHz. The input n
PGA Front End (2.5VP-P or 1.667VP-P Input Range)
range of the ADC can be optimized with the PGA front end. n
380MHz Full Power Bandwidth S/H
The LTC2201 is perfect for demanding app lications, with n
Optional Internal Dither
AC performance that includes 81.6dB SNR and 100dB n
Optional Data Output Randomizer
spurious free dynamic range (SFDR). Maximum DC specs n Single 3.3V Supply include ±5LSB INL, ±1LSB DNL (no missing codes). n Power Dissipation: 211mW n Clock Duty Cycle Stabilizer A separate output power supply allows the CMOS output n Out-of-Range Indicator swing to range from 0.5V to 3.6V. n Pin Compatible Family A single-ended CLK input controls converter operation. An 25Msps: LTC2203 (16-Bit) optional clock duty cycle stabilizer allows high performance 10Msps: LTC2202 (16-Bit) at full speed with a wide range of clock duty cycles. n 48-Pin (7mm × 7mm) QFN Package L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIONS
n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION Integral Nonlinearity (INL)
3.3V
vs Output Code
SENSE 2.0 OV 1.25V INTERNAL ADC DD VCM 0.5V TO 3.6V COMMON MODE REFERENCE 1.5 2.2μF BIAS VOLTAGE GENERATOR 1μF 1.0 OF A + IN 0.5 + CLKOUT+ 16-BIT CORRECTION OUTPUT CLKOUT– ANALOG S/H PIPELINED LOGIC AND DRIVERS CMOS 0.0 INPUT AMP D15 ADC CORE SHIFT REGISTER OUTPUTS – – t A t IN –0.5 t INL ERROR (LSB) D0 OGND –1.0 CLOCK/DUTY –1.5 CYCLE V 3.3V DD CONTROL 1μF 1μF 1μF GND –2.0 0 16384 32768 49152 65536 CODE CLK PGA SHDN DITH MODE OE RAND 2201 TA02 2201 TA01 ADC CONTROL INPUTS 2201f 1
FEATURES DESCRIPTION
n
Sample Rate: 20Msps
The LTC®2201 is a 20Msps, sampling 16-bit A/D converter n
81.6dB SNR and 100dB SFDR (2.5V Range)
designed for digitizing high frequen cy, wide dynamic range n
90dB SFDR at 70MHz (1.667VP-P Input Range)
signals with input frequencies up to 380MHz. The input n
PGA Front End (2.5VP-P or 1.667VP-P Input Range)
range of the ADC can be optimized with the PGA front end. n
380MHz Full Power Bandwidth S/H
The LTC2201 is perfect for demanding app lications, with n
Optional Internal Dither
AC performance that includes 81.6dB SNR and 100dB n
Optional Data Output Randomizer
spurious free dynamic range (SFDR). Maximum DC specs n Single 3.3V Supply include ±5LSB INL, ±1LSB DNL (no missing codes). n Power Dissipation: 211mW n Clock Duty Cycle Stabilizer A separate output power supply allows the CMOS output n Out-of-Range Indicator swing to range from 0.5V to 3.6V. n Pin Compatible Family A single-ended CLK input controls converter operation. An 25Msps: LTC2203 (16-Bit) optional clock duty cycle stabilizer allows high performance 10Msps: LTC2202 (16-Bit) at full speed with a wide range of clock duty cycles. n 48-Pin (7mm × 7mm) QFN Package L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIONS
n Telecommunications n Receivers n Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE
TYPICAL APPLICATION Integral Nonlinearity (INL)
3.3V
vs Output Code
SENSE 2.0 OV 1.25V INTERNAL ADC DD VCM 0.5V TO 3.6V COMMON MODE REFERENCE 1.5 2.2μF BIAS VOLTAGE GENERATOR 1μF 1.0 OF A + IN 0.5 + CLKOUT+ 16-BIT CORRECTION OUTPUT CLKOUT– ANALOG S/H PIPELINED LOGIC AND DRIVERS CMOS 0.0 INPUT AMP D15 ADC CORE SHIFT REGISTER OUTPUTS – – t A t IN –0.5 t INL ERROR (LSB) D0 OGND –1.0 CLOCK/DUTY –1.5 CYCLE V 3.3V DD CONTROL 1μF 1μF 1μF GND –2.0 0 16384 32768 49152 65536 CODE CLK PGA SHDN DITH MODE OE RAND 2201 TA02 2201 TA01 ADC CONTROL INPUTS 2201f 1