Datasheet LTC2159 (Analog Devices)
| Hersteller | Analog Devices |
| Beschreibung | 16-Bit, 20Msps Low Power ADC |
| Seiten / Seite | 32 / 1 — FeaTures. DescripTion. applicaTions. Typical applicaTion. Integral … |
| Dateiformat / Größe | PDF / 532 Kb |
| Dokumentensprache | Englisch |
FeaTures. DescripTion. applicaTions. Typical applicaTion. Integral Non-Linearity (INL)
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LTC2159 16-Bit, 20Msps Low Power ADC
FeaTures DescripTion
n 77dB SNR The LTC®2159 is a sampling 16-bit A/D converter designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 43mW It is perfect for demanding communications applications n Single 1.8V Supply with AC performance that includes 77dB SNR and 90dB n CMOS, DDR CMOS, or DDR LVDS Outputs spurious free dynamic range (SFDR). Ultralow jitter of n Selectable Input Ranges: 1VP-P to 2VP-P 0.07psRMS allows undersampling of IF frequencies with n 550MHz Full Power Bandwidth S/H excellent noise performance. n Optional Data Output Randomizer DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is 3.2LSBRMS. n Serial SPI Port for Configuration n 48-Lead (7mm × 7mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V
Integral Non-Linearity (INL)
VDD OVDD 4.0 3.0 ANALOG 16-BIT 2.0 S/H INPUT ADC CORE D15 1.0 • CMOS OUTPUT • DDR CMOS OR 0 DRIVERS • DDR LVDS D0 OUTPUTS –1.0 INL ERROR (LSB) 20MHz –2.0 CLOCK CONTROL CLOCK –3.0 –4.0 0 16384 32768 49152 65536 2159 TA01a GND OGND OUTPUT CODE 2159 TA01b 2159f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts
FeaTures DescripTion
n 77dB SNR The LTC®2159 is a sampling 16-bit A/D converter designed n 90dB SFDR for digitizing high frequency, wide dynamic range signals. n Low Power: 43mW It is perfect for demanding communications applications n Single 1.8V Supply with AC performance that includes 77dB SNR and 90dB n CMOS, DDR CMOS, or DDR LVDS Outputs spurious free dynamic range (SFDR). Ultralow jitter of n Selectable Input Ranges: 1VP-P to 2VP-P 0.07psRMS allows undersampling of IF frequencies with n 550MHz Full Power Bandwidth S/H excellent noise performance. n Optional Data Output Randomizer DC specs include ±2LSB INL (typ), ±0.5LSB DNL (typ) n Optional Clock Duty Cycle Stabilizer and no missing codes over temperature. The transition n Shutdown and Nap Modes noise is 3.2LSBRMS. n Serial SPI Port for Configuration n 48-Lead (7mm × 7mm) QFN Package The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to
applicaTions
range from 1.2V to 1.8V. n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An optional clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V 1.8V
Integral Non-Linearity (INL)
VDD OVDD 4.0 3.0 ANALOG 16-BIT 2.0 S/H INPUT ADC CORE D15 1.0 • CMOS OUTPUT • DDR CMOS OR 0 DRIVERS • DDR LVDS D0 OUTPUTS –1.0 INL ERROR (LSB) 20MHz –2.0 CLOCK CONTROL CLOCK –3.0 –4.0 0 16384 32768 49152 65536 2159 TA01a GND OGND OUTPUT CODE 2159 TA01b 2159f 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Electrical Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Functional Block Diagram Applications Information Typical Applications Package Description Typical Application Related Parts