Datasheet LTC1864L, LTC1865L (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | µPower, 3V, 16-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| Seiten / Seite | 16 / 7 — PI FU CTIO S. LTC1864L. VREF (Pin 1):. SDO (Pin 6):. IN+, IN– (Pins 2, … |
| Dateiformat / Größe | PDF / 366 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. LTC1864L. VREF (Pin 1):. SDO (Pin 6):. IN+, IN– (Pins 2, 3):. SCK (Pin 7):. GND (Pin 4):. VCC (Pin 8):. CONV (Pin 5):
Modelllinie für dieses Datenblatt
- LTC1864LACMS8#PBF LTC1864LACMS8#PBF LTC1864LACMS8#TRPBF LTC1864LACMS8#TRPBF LTC1864LACS8#PBF LTC1864LACS8#PBF LTC1864LACS8#TRPBF LTC1864LACS8#TRPBF LTC1864LAIMS8#PBF LTC1864LAIMS8#PBF LTC1864LAIMS8#TRPBF LTC1864LAIMS8#TRPBF LTC1864LAIS8#PBF LTC1864LAIS8#PBF LTC1864LAIS8#TRPBF LTC1864LAIS8#TRPBF LTC1864LCMS8#PBF LTC1864LCMS8#PBF LTC1864LCMS8#TRPBF LTC1864LCMS8#TRPBF LTC1864LCS8#PBF LTC1864LCS8#PBF LTC1864LCS8#TRPBF LTC1864LCS8#TRPBF LTC1864LIMS8#PBF LTC1864LIMS8#PBF LTC1864LIMS8#TRPBF LTC1864LIMS8#TRPBF LTC1864LIS8#PBF LTC1864LIS8#PBF LTC1864LIS8#TRPBF LTC1864LIS8#TRPBF
- LTC1865LACMS#PBF LTC1865LACMS#PBF LTC1865LACMS#TRPBF LTC1865LACMS#TRPBF LTC1865LACS8#PBF LTC1865LACS8#PBF LTC1865LACS8#TRPBF LTC1865LACS8#TRPBF LTC1865LAIMS#PBF LTC1865LAIMS#PBF LTC1865LAIMS#TRPBF LTC1865LAIMS#TRPBF LTC1865LAIS8#PBF LTC1865LAIS8#PBF LTC1865LAIS8#TRPBF LTC1865LAIS8#TRPBF LTC1865LCMS#PBF LTC1865LCMS#PBF LTC1865LCMS#TRPBF LTC1865LCMS#TRPBF LTC1865LCS8#PBF LTC1865LCS8#PBF LTC1865LCS8#TRPBF LTC1865LCS8#TRPBF LTC1865LIMS#PBF LTC1865LIMS#PBF LTC1865LIMS#TRPBF LTC1865LIMS#TRPBF LTC1865LIS8#PBF LTC1865LIS8#PBF LTC1865LIS8#TRPBF LTC1865LIS8#TRPBF
Textversion des Dokuments
LTC1864L/LTC1865L
U U U PI FU CTIO S LTC1864L VREF (Pin 1):
Reference Input. The reference input defines down. A logic low on this input enables the SDO pin, the span of the A/D converter and must be kept free of allowing the data to be shifted out. noise with respect to GND.
SDO (Pin 6):
Digital Data Output. The A/D conversion
IN+, IN– (Pins 2, 3):
Analog Inputs. These inputs must be result is shifted out of this pin. free of noise with respect to GND.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes the
GND (Pin 4):
Analog Ground. GND should be tied directly serial data transfer. to an analog ground plane.
VCC (Pin 8):
Positive Supply. This supply must be kept
CONV (Pin 5):
Convert Input. A logic high on this input free of noise and ripple by bypassing directly to the starts the A/D conversion process. If the CONV input is left analog ground plane. high after the A/D conversion is finished, the part powers
LTC1865L (MSOP Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDO (Pin 7):
Digital Data Output. The A/D conversion starts the A/D conversion process. If the CONV input is left result is shifted out of this output. high after the A/D conversion is finished, the part powers
SCK (Pin 8):
Shift Clock Input. This clock synchronizes the down. A logic low on this input enables the SDO pin, serial data transfer. allowing the data to be shifted out.
V CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
CC (Pin 9):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the be free of noise with respect to AGND. analog ground plane.
AGND (Pin 4):
Analog Ground. AGND should be tied
V
directly to an analog ground plane.
REF (Pin 10):
Reference Input. The reference input de- fines the span of the A/D converter and must be kept free
DGND (Pin 5):
Digital Ground. DGND should be tied of noise with respect to AGND. directly to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D configuration word is shifted into this input.
LTC1865L (SO-8 Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDI (Pin 5):
Digital Data Input. The A/D configuration starts the A/D conversion process. If the CONV input is left word is shifted into this input. high after the A/D conversion is finished, the part powers
SDO (Pin 6):
Digital Data Output. The A/D conversion down. A logic low on this input enables the SDO pin, result is shifted out of this output. allowing the data to be shifted out.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes the
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must serial data transfer. be free of noise with respect to GND.
V GND (Pin 4):
Analog Ground. GND should be tied directly
CC (Pin 8):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the to an analog ground plane. analog ground plane. VREF is tied internally to this pin. sn18645L 18645Lfs 7
U U U PI FU CTIO S LTC1864L VREF (Pin 1):
Reference Input. The reference input defines down. A logic low on this input enables the SDO pin, the span of the A/D converter and must be kept free of allowing the data to be shifted out. noise with respect to GND.
SDO (Pin 6):
Digital Data Output. The A/D conversion
IN+, IN– (Pins 2, 3):
Analog Inputs. These inputs must be result is shifted out of this pin. free of noise with respect to GND.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes the
GND (Pin 4):
Analog Ground. GND should be tied directly serial data transfer. to an analog ground plane.
VCC (Pin 8):
Positive Supply. This supply must be kept
CONV (Pin 5):
Convert Input. A logic high on this input free of noise and ripple by bypassing directly to the starts the A/D conversion process. If the CONV input is left analog ground plane. high after the A/D conversion is finished, the part powers
LTC1865L (MSOP Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDO (Pin 7):
Digital Data Output. The A/D conversion starts the A/D conversion process. If the CONV input is left result is shifted out of this output. high after the A/D conversion is finished, the part powers
SCK (Pin 8):
Shift Clock Input. This clock synchronizes the down. A logic low on this input enables the SDO pin, serial data transfer. allowing the data to be shifted out.
V CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must
CC (Pin 9):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the be free of noise with respect to AGND. analog ground plane.
AGND (Pin 4):
Analog Ground. AGND should be tied
V
directly to an analog ground plane.
REF (Pin 10):
Reference Input. The reference input de- fines the span of the A/D converter and must be kept free
DGND (Pin 5):
Digital Ground. DGND should be tied of noise with respect to AGND. directly to an analog ground plane.
SDI (Pin 6):
Digital Data Input. The A/D configuration word is shifted into this input.
LTC1865L (SO-8 Package) CONV (Pin 1):
Convert Input. A logic high on this input
SDI (Pin 5):
Digital Data Input. The A/D configuration starts the A/D conversion process. If the CONV input is left word is shifted into this input. high after the A/D conversion is finished, the part powers
SDO (Pin 6):
Digital Data Output. The A/D conversion down. A logic low on this input enables the SDO pin, result is shifted out of this output. allowing the data to be shifted out.
SCK (Pin 7):
Shift Clock Input. This clock synchronizes the
CH0, CH1 (Pins 2, 3):
Analog Inputs. These inputs must serial data transfer. be free of noise with respect to GND.
V GND (Pin 4):
Analog Ground. GND should be tied directly
CC (Pin 8):
Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the to an analog ground plane. analog ground plane. VREF is tied internally to this pin. sn18645L 18645Lfs 7