Datasheet LTC1864L, LTC1865L (Analog Devices) - 10

LTC1864L/LTC1865L
U U W U APPLICATIO S I FOR ATIO LTC1865L OPERATION
single-ended mode, all input channels are measured with respect to GND. A zero code will occur when the “+” input
Operating Sequence
minus the “–” input equals zero. Full scale occurs when The LTC1865L conversion cycle begins with the rising the “+” input minus the “–” input equals VREF minus edge of CONV. After a period equal to t 1LSB. See Figure 5. Both the “+” and “–” inputs are CONV, the conver- sion is finished. If CONV is left high after this time, the sampled at the same time so common mode noise is LTC1865L goes into sleep mode drawing only leakage rejected. The input span in the SO-8 package is fixed at current. The LTC1865L’s 2-bit data word is clocked into VREF = VCC. If the “–” input in differential mode is the SDI input on the rising edge of SCK after CONV goes grounded, a rail-to-rail input span will result on the “+” low. Additional inputs on the SDI pin are then ignored until input. the next CONV cycle. The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the
Reference Input
falling SCK edge and captured on the rising SCK edge in The reference input of the LTC1865L SO-8 package is both transmitting and receiving systems. The data is internally tied to VCC. The span of the A/D converter is transmitted and received simultaneously (full duplex). therefore equal to VCC. The voltage on the reference input After completing the data transfer, if further SCK clocks of the LTC1865L MSOP package defines the span of the are applied with CONV low, SDO will output zeros indefi- A/D converter. The LTC1865L MSOP package can operate nitely. See Figure 4. with reference voltages from 1V to VCC.
Analog Inputs Table 1. Multiplexer Channel Selection
The two bits of the input word (SDI) assign the MUX
MUX ADDRESS CHANNEL # SGL/DIFF ODD/SIGN 0 1 GND
configuration for the next requested conversion. For a SINGLE-ENDED 1 0 + – given channel selection, the converter will measure the MUX MODE 1 1 + – voltage between the two channels indicated by the DIFFERENTIAL 0 0 + – “+” and “–” signs in the selected row of Table 1. In MUX MODE 0 1 – + 1864 TBL1 CONV tSMPL tCONV SLEEP MODE SDI DON’T CARE S/D O/S DON’T CARE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCK DON'T CARE SDO B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* Hi-Z Hi-Z *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY 1864 F04
Figure 4. LTC1865L Operating Sequence
sn18645L 18645Lfs 10