Datasheet LTC1417 (Analog Devices) - 9

LTC1417
U U W U APPLICATIONS INFORMATION CONVERSION DETAILS
summing junction. This input charge is successively compared with the binary weighted charges supplied by The LTC1417 uses a successive approximation algorithm the differential capacitive DAC. Bit decisions are made by and an internal sample-and-hold circuit to convert an the high speed comparator. At the end of a conversion, the analog signal to a 14-bit serial output. The ADC is com- differential DAC output balances the A + and A – input plete with a precision reference and an internal clock. The IN IN charges. The SAR contents (a 14-bit data word) that control logic provides easy interface to microprocessors represent the difference of A + and A – are output and DSPs (please refer to Digital Interface section for the IN IN through the serial pin D data format). OUT. Conversion start is controlled by the CONVST input. At the
DC Performance
start of the conversion, the successive approximation One way of measuring the transition noise associated with register (SAR) is reset. Once a conversion cycle has a high resolution ADC is to use a technique where a DC begun, it cannot be restarted. signal is applied to the input of the ADC and the resulting During the conversion, the internal differential 14-bit output codes are collected over a large number of conver- capacitive DAC output is sequenced by the SAR from the sions. For example in Figure 2, the distribution of output most significant bit (MSB) to the least significant bit (LSB). code is shown for a DC input that has been digitized 4096 Referring to Figure 1, the A + – times. The distribution is Gaussian and the RMS code IN and AIN inputs are con- nected to the sample-and-hold capacitors (C transition is about 0.33LSB. SAMPLE) dur- ing the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum 4000 delay of 500ns will provide enough time for the sample- 3500 and-hold capacitors to acquire the analog signal. During 3000 the convert phase, the comparator zeroing switches open, 2500 placing the comparator in compare mode. The input 2000 switches connect the CSAMPLE capacitors to ground, COUNTS transferring the differential analog input charge onto the 1500 1000 500 C + SAMPLE 0 SAMPLE –2 –1 0 1 2 A + IN CODE HOLD ZEROING SWITCHES 1417 F02 C – SAMPLE HOLD SAMPLE A –
Figure 2. Histogram for 4096 Conversions
IN HOLD HOLD C +
DYNAMIC PERFORMANCE
DAC + The LTC1417 has excellent high speed sampling capabil- C – DAC COMP V + DAC ity. FFT (Fast Fourier Transform) test techniques are used – to test the ADC’s frequency response, distortion and noise performance at the rated throughput. By applying V – DAC 14 SHIFT SAR D a low distortion sine wave and analyzing the digital output REGISTER OUT using an FFT algorithm, the ADC’s spectral content can be 1417 F01 examined for frequencies beyond the fundamental.
Figure 1. Simplified Block Diagram
Figure 3 shows a typical LTC1417 FFT plot. sn1417 1417fas 9