Datasheet LTC1417 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O |
| Seiten / Seite | 32 / 8 — PIN FUNCTIONS. CONVST (Pin 13):. VSS (Pin 15):. BUSY (Pin 14):. VDD (Pin … |
| Dateiformat / Größe | PDF / 413 Kb |
| Dokumentensprache | Englisch |
PIN FUNCTIONS. CONVST (Pin 13):. VSS (Pin 15):. BUSY (Pin 14):. VDD (Pin 16):. TEST CIRCUITS. Load Circuits for Access Timing
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LTC1417
U U U PIN FUNCTIONS CONVST (Pin 13):
Conversion Start Signal. This active
VSS (Pin 15):
Negative Supply, –5V for Bipolar Operation. low signal starts a conversion on its falling edge. Bypass to AGND using 10µF tantalum in parallel with
BUSY (Pin 14):
The BUSY output shows the converter 0.1µF ceramic. Analog ground for unipolar operation. status. It is low when a conversion is in progress.
VDD (Pin 16):
5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DOUT DOUT DOUT DOUT 1k CL CL 1k 30pF 30pF DGND DGND A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL A) VOH TO HI-Z B) VOL TO HI-Z 1417 TC02 1417 TC01
U U W FUNCTIONAL BLOCK DIAGRA
CSAMPLE 1 A + IN 16 VDD CSAMPLE V 2 15 SS A – IN (0V FOR UNIPOLAR MODE 8k 3 ZEROING SWITCHES –5V FOR BIPOLAR MODE) VREF 2.5V REF + REF AMP 14-BIT CAPACITIVE DAC COMP – REFCOMP 4 (4.096V) 14 SUCCESSIVE APPROXIMATION 9 SHIFT REGISTER DOUT 5 REGISTER AGND 7 INTERNAL MUX SCLK 10 CLOCK CONTROL LOGIC DGND 6 11 13 12 8 14 1417 BD EXTCLKIN SHDN CONVST RD CLKOUT BUSY sn1417 1417fas 8
U U U PIN FUNCTIONS CONVST (Pin 13):
Conversion Start Signal. This active
VSS (Pin 15):
Negative Supply, –5V for Bipolar Operation. low signal starts a conversion on its falling edge. Bypass to AGND using 10µF tantalum in parallel with
BUSY (Pin 14):
The BUSY output shows the converter 0.1µF ceramic. Analog ground for unipolar operation. status. It is low when a conversion is in progress.
VDD (Pin 16):
5V Positive Supply. Bypass to AGND with 10µF tantalum in parallel with 0.1µF ceramic.
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DOUT DOUT DOUT DOUT 1k CL CL 1k 30pF 30pF DGND DGND A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL A) VOH TO HI-Z B) VOL TO HI-Z 1417 TC02 1417 TC01
U U W FUNCTIONAL BLOCK DIAGRA
CSAMPLE 1 A + IN 16 VDD CSAMPLE V 2 15 SS A – IN (0V FOR UNIPOLAR MODE 8k 3 ZEROING SWITCHES –5V FOR BIPOLAR MODE) VREF 2.5V REF + REF AMP 14-BIT CAPACITIVE DAC COMP – REFCOMP 4 (4.096V) 14 SUCCESSIVE APPROXIMATION 9 SHIFT REGISTER DOUT 5 REGISTER AGND 7 INTERNAL MUX SCLK 10 CLOCK CONTROL LOGIC DGND 6 11 13 12 8 14 1417 BD EXTCLKIN SHDN CONVST RD CLKOUT BUSY sn1417 1417fas 8