Datasheet LTC1412 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 12-Bit, 3Msps, Sampling A/D Converter |
| Seiten / Seite | 16 / 7 — FUNCTIONAL BLOCK DIAGRA. TEST CIRCUITS. Load Circuits for Access Timing. … |
| Dateiformat / Größe | PDF / 347 Kb |
| Dokumentensprache | Englisch |
FUNCTIONAL BLOCK DIAGRA. TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay
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LTC1412
U U W FUNCTIONAL BLOCK DIAGRA
CSAMPLE A + IN AVDD CSAMPLE DVDD A – IN 2k ZEROING SWITCHES VREF 2.5V REF + REF AMP 12-BIT CAPACITIVE DAC COMP – REFCOMP (4.06V) 12 SUCCESSIVE APPROXIMATION OUTPUT • D11 • REGISTER LATCHES • D0 AGND OV INTERNAL DD CONTROL LOGIC DGND CLOCK OGND 1412 BD CONVST CS BUSY
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL A) VOH TO HI-Z B) VOL TO HI-Z 1412 TC02 1412 TC01
U U W U APPLICATIONS INFORMATION Conversion Details
approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. The LTC1412 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an During the conversion, the internal differential 12-bit analog signal to a 12-bit parallel output. The ADC is capacitive DAC output is sequenced by the SAR from the complete with a precision reference and an internal clock. most significant bit (MSB) to the least significant bit The control logic provides easy interface to microproces- (LSB). Referring to Figure 1, the A + – IN and AIN inputs are sors and DSPs. (Please refer to the Digital Interface connected to the sample-and-hold capacitors (CSAMPLE) section for the data format.) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a Conversion start is controlled by the CS and CONVST minimum delay of 50ns will provide enough time for the inputs. At the start of the conversion the successive 7
U U W FUNCTIONAL BLOCK DIAGRA
CSAMPLE A + IN AVDD CSAMPLE DVDD A – IN 2k ZEROING SWITCHES VREF 2.5V REF + REF AMP 12-BIT CAPACITIVE DAC COMP – REFCOMP (4.06V) 12 SUCCESSIVE APPROXIMATION OUTPUT • D11 • REGISTER LATCHES • D0 AGND OV INTERNAL DD CONTROL LOGIC DGND CLOCK OGND 1412 BD CONVST CS BUSY
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DBN DBN DBN DBN 1k CL CL 1k 100pF 100pF A) HI-Z TO VOH AND VOL TO VOH B) HI-Z TO VOL AND VOH TO VOL A) VOH TO HI-Z B) VOL TO HI-Z 1412 TC02 1412 TC01
U U W U APPLICATIONS INFORMATION Conversion Details
approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. The LTC1412 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an During the conversion, the internal differential 12-bit analog signal to a 12-bit parallel output. The ADC is capacitive DAC output is sequenced by the SAR from the complete with a precision reference and an internal clock. most significant bit (MSB) to the least significant bit The control logic provides easy interface to microproces- (LSB). Referring to Figure 1, the A + – IN and AIN inputs are sors and DSPs. (Please refer to the Digital Interface connected to the sample-and-hold capacitors (CSAMPLE) section for the data format.) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a Conversion start is controlled by the CS and CONVST minimum delay of 50ns will provide enough time for the inputs. At the start of the conversion the successive 7