Datasheet LTC1411 (Analog Devices) - 8
| Hersteller | Analog Devices |
| Beschreibung | Single Supply 14-Bit 2.5Msps ADC |
| Seiten / Seite | 16 / 8 — TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output … |
| Dateiformat / Größe | PDF / 233 Kb |
| Dokumentensprache | Englisch |
TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay. APPLICATIO S I FOR ATIO
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1411
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DN DN DN DN 1k CL CL 1k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1411 TC01 1411 TC02
U U W U APPLICATIO S I FOR ATIO CONVERSION DETAILS
During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the The LTC1411 uses a successive approximation algorithm most significant bit (MSB) to the least significant bit and an internal sample-and-hold circuit to convert an (LSB). The input is successively compared with the binary analog signal to a 14-bit parallel output. The ADC is weighted charges supplied by the differential capacitive complete with a precision reference, internal clock and a DAC. Bit decisions are made by a high speed comparator. programmable input range. The device is easy to interface At the end of a conversion, the DAC output balances the with microprocessors and DSPs. (Please refer to the analog input (A + – A –). The SAR contents (a 14-bit Digital Interface section for the data format.) IN IN data word) which represents the difference of A + IN and Conversions are started by a falling edge on the CONVST A – IN are loaded into the 14-bit output latches. input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, the ADC acquires the
DYNAMIC PERFORMANCE
analog input in preparation for the next conversion. In the acquire phase, a minimum time of 100ns will provide The LTC1411 has excellent high speed sampling capabil- enough time for the sample-and-hold capacitors to ac- ity. FFT (Fast Fourier Transform) test techniques are used quire the analog signal. to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine 10 30 AVP DVP OV + DD wave and analyzing the digital output using an FFT algo- AIN 29 1 rithm, the ADC’s spectral content can be examined for A – IN OGND 28 2 frequencies outside the fundamental. Figure 2a shows a D13 12 typical LTC1411 FFT plot. + 14-BIT 14 ADC – •
Signal-to-Noise
• OUTPUT • The signal-to-(noise + distortion) ratio [S/N + D)] is the INTERNAL DRIVERS ratio between the RMS amplitude of the fundamental input CLOCK D0 25 frequency to the RMS amplitude of all other frequency BUSY 27 components at the A/D output. The output is band limited OTR CONTROL LOGIC 26 to frequencies from the above DC and below half the sampling frequency. Figure 2a shows a typical spectral SLP NAP content with a 2.5MHz sampling rate and a 100kHz input. PGA0 PGA1 CONVST DGND 36 35 34 33 32 31 1411 F01 The dynamic performance holds well to higher input
Figure 1. Simplified Block Diagram
frequencies (see Figure 2b). 1411f 8
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DN DN DN DN 1k CL CL 1k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1411 TC01 1411 TC02
U U W U APPLICATIO S I FOR ATIO CONVERSION DETAILS
During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the The LTC1411 uses a successive approximation algorithm most significant bit (MSB) to the least significant bit and an internal sample-and-hold circuit to convert an (LSB). The input is successively compared with the binary analog signal to a 14-bit parallel output. The ADC is weighted charges supplied by the differential capacitive complete with a precision reference, internal clock and a DAC. Bit decisions are made by a high speed comparator. programmable input range. The device is easy to interface At the end of a conversion, the DAC output balances the with microprocessors and DSPs. (Please refer to the analog input (A + – A –). The SAR contents (a 14-bit Digital Interface section for the data format.) IN IN data word) which represents the difference of A + IN and Conversions are started by a falling edge on the CONVST A – IN are loaded into the 14-bit output latches. input. Once a conversion cycle has begun, it cannot be restarted. Between conversions, the ADC acquires the
DYNAMIC PERFORMANCE
analog input in preparation for the next conversion. In the acquire phase, a minimum time of 100ns will provide The LTC1411 has excellent high speed sampling capabil- enough time for the sample-and-hold capacitors to ac- ity. FFT (Fast Fourier Transform) test techniques are used quire the analog signal. to test the ADC’s frequency response, distortion and noise at the rated throughput. By applying a low distortion sine 10 30 AVP DVP OV + DD wave and analyzing the digital output using an FFT algo- AIN 29 1 rithm, the ADC’s spectral content can be examined for A – IN OGND 28 2 frequencies outside the fundamental. Figure 2a shows a D13 12 typical LTC1411 FFT plot. + 14-BIT 14 ADC – •
Signal-to-Noise
• OUTPUT • The signal-to-(noise + distortion) ratio [S/N + D)] is the INTERNAL DRIVERS ratio between the RMS amplitude of the fundamental input CLOCK D0 25 frequency to the RMS amplitude of all other frequency BUSY 27 components at the A/D output. The output is band limited OTR CONTROL LOGIC 26 to frequencies from the above DC and below half the sampling frequency. Figure 2a shows a typical spectral SLP NAP content with a 2.5MHz sampling rate and a 100kHz input. PGA0 PGA1 CONVST DGND 36 35 34 33 32 31 1411 F01 The dynamic performance holds well to higher input
Figure 1. Simplified Block Diagram
frequencies (see Figure 2b). 1411f 8