Datasheet LTC1411 (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | Single Supply 14-Bit 2.5Msps ADC |
| Seiten / Seite | 16 / 7 — PI FU CTIO S. DVP (Pin 30):. Table 1. Input Spans for LTC1411. INPUT. … |
| Dateiformat / Größe | PDF / 233 Kb |
| Dokumentensprache | Englisch |
PI FU CTIO S. DVP (Pin 30):. Table 1. Input Spans for LTC1411. INPUT. REFCOM2. PGA0. PGA1. LEVEL. SPAN. VOLTAGE. DGND (Pin 31):
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LTC1411
U U U PI FU CTIO S DVP (Pin 30):
5V Digital Power Supply Pin. Bypass to
Table 1. Input Spans for LTC1411
OGND with a 10µF tantalum capacitor.
INPUT REFCOM2 PGA0 PGA1 LEVEL SPAN VOLTAGE DGND (Pin 31):
Digital Ground. 5V 5V 0dB ±1.8V 4V
CONVST (Pin 32):
Conversion Start Signal. This active 5V 0V – 3dB ±1.28V 2.9V low signal starts a conversion on its falling edge. 0V 5V – 6dB ±0.9V 2V 0V 0V – 9dB ±0.64V 1.45V
PGA1, PGA0 (Pins 33, 34):
Logic Inputs for Program- mable Input Range. This ADC has four input ranges (or
NAP (Pin 35):
Nap Input. Driving this pin low will put the four REFCOM2 voltages) controlled by these two pins. ADC in the Nap mode and will reduce the supply current to For the logic inputs applied to PGA0 and PGA1, the 2mA and the internal reference will remain active. following summarizes the gain levels and the analog input range with A –
SLP (Pin 36):
Sleep Input. Driving this pin low will put the IN tied to 2.5V. ADC in the Sleep mode and the ADC draws less than 1µA of supply current.
UU U W TYPICAL CO ECTIO DIAGRA
5V + 10 30 AVP DVP OV + DD AIN 29 5V OR 3V 1 + A – IN 2 OGND 28 D13 2.5V 12 REFOUT + 3 BANDGAP + 14-BIT 22 REFERENCE 14 µF* ADC REFIN – • 4 • 5k OUTPUT • DRIVERS 5k 2k D0 25 INTERNAL BUSY REFCOM1 CLOCK 27 + 5 OTR 10µF 26 REFCOM2 + X1.62/ 6 CONTROL LOGIC X1.15 10µF 7, 8, 9 AGND AVM SLP NAP PGA0 PGA1 CONVST DGND 1411 TA01 11 36 35 34 33 32 31 *A 22µF CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE A – IN 1411f 7
U U U PI FU CTIO S DVP (Pin 30):
5V Digital Power Supply Pin. Bypass to
Table 1. Input Spans for LTC1411
OGND with a 10µF tantalum capacitor.
INPUT REFCOM2 PGA0 PGA1 LEVEL SPAN VOLTAGE DGND (Pin 31):
Digital Ground. 5V 5V 0dB ±1.8V 4V
CONVST (Pin 32):
Conversion Start Signal. This active 5V 0V – 3dB ±1.28V 2.9V low signal starts a conversion on its falling edge. 0V 5V – 6dB ±0.9V 2V 0V 0V – 9dB ±0.64V 1.45V
PGA1, PGA0 (Pins 33, 34):
Logic Inputs for Program- mable Input Range. This ADC has four input ranges (or
NAP (Pin 35):
Nap Input. Driving this pin low will put the four REFCOM2 voltages) controlled by these two pins. ADC in the Nap mode and will reduce the supply current to For the logic inputs applied to PGA0 and PGA1, the 2mA and the internal reference will remain active. following summarizes the gain levels and the analog input range with A –
SLP (Pin 36):
Sleep Input. Driving this pin low will put the IN tied to 2.5V. ADC in the Sleep mode and the ADC draws less than 1µA of supply current.
UU U W TYPICAL CO ECTIO DIAGRA
5V + 10 30 AVP DVP OV + DD AIN 29 5V OR 3V 1 + A – IN 2 OGND 28 D13 2.5V 12 REFOUT + 3 BANDGAP + 14-BIT 22 REFERENCE 14 µF* ADC REFIN – • 4 • 5k OUTPUT • DRIVERS 5k 2k D0 25 INTERNAL BUSY REFCOM1 CLOCK 27 + 5 OTR 10µF 26 REFCOM2 + X1.62/ 6 CONTROL LOGIC X1.15 10µF 7, 8, 9 AGND AVM SLP NAP PGA0 PGA1 CONVST DGND 1411 TA01 11 36 35 34 33 32 31 *A 22µF CAPACITOR IS NEEDED IF REFOUT IS USED TO DRIVE A – IN 1411f 7