Datasheet LTC1400 (Analog Devices) - 7

LTC1400
U U W U APPLICATIO S I FOR ATIO Conversion Details Dynamic Performance
The LTC1400 uses a successive approximation algorithm The LTC1400 has excel ent high speed sampling capability. and an internal sample-and-hold circuit to convert an FFT (Fast Fourier Transform) test techniques are used to analog signal to a 12-bit serial output based on a preci- test the ADC’s frequency response, distortion and noise sion internal reference. The control logic provides easy at the rated throughput. By applying a low distortion interface to microprocessors and DSPs through 3-wire sine wave and analyzing the digital output using an FFT connections. algorithm, the ADC’s spectral content can be examined for A rising edge on the CONV input starts a conversion. At frequencies outside the fundamental. Figure 2a shows a the start of a conversion the successive approximation typical LTC1400 FFT plot. register (SAR) is reset. Once a conversion cycle has begun
Signal-to-Noise Ratio
it cannot be restarted. The signal-to-noise plus distortion ratio [S/(N + D)] is the During conversion, the internal 12-bit capacitive DAC ratio between the RMS amplitude of the fundamental input output is sequenced by the SAR from the most significant frequency to the RMS amplitude of all other frequency bit (MSB) to the least significant bit (LSB). Referring to components at the A/D output. The output is band limited Figure 1, the AIN input connects to the sample-and-hold to frequencies from DC to half the sampling frequency. capacitor during the acquired phase and the comparator Figure 2a shows a typical spectral content with a 400kHz offset is nulled by the feedback switch. In this acquire sampling rate and a 100kHz input. The dynamic perfor- phase, it typically takes 200ns for the sample-and-hold mance is excellent for input frequencies up to the Nyquist capacitor to acquire the analog signal. During the convert limit of 200kHz as shown in Figure 2b. phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switches 0 –10 fSAMPLE = 400kHz connect C f SAMPLE to ground, injecting the analog input IN = 94.824kHz –20 SINAD = 72.5dB charge onto the summing junction. This input charge is –30 THD = –82dB successively compared with the binary-weighted charges –40 supplied by the capacitive DAC. Bit decisions are made by –50 –60 the high speed comparator. At the end of a conversion, –70 the DAC output balances the AIN input charge. The SAR AMPLITUDE (dB) –80 contents (a 12-bit data word) which represent the input –90 –100 voltage, are output through the serial pin DOUT. –110 –120 0 20 40 60 80 100 120 140 160 180 200 SAMPLE FREQUENCY (kHz) 1400 F02a S1 CSAMPLE SAMPLE –
Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT
AIN
Plot with 100kHz Input Frequency in Bipolar Mode
COMP HOLD DAC +
Effective Number of Bits
CDAC The effective number of bits (ENOBs) is a measurement S V of the effective resolution of an ADC and is directly related DAC A R to the S/(N + D) by the equation: DOUT S / N ( +D)– .176 1400 F01 N= 6.02
Figure 1. AIN Input
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