Datasheet LTC1283 (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 3V Single Chip 10-Bit Data Acquisition System |
| Seiten / Seite | 24 / 6 — TYPICAL PERFOR A CE CH. ARA TERISTICS. Sample-and-Hold Acquisition. Input … |
| Dateiformat / Größe | PDF / 352 Kb |
| Dokumentensprache | Englisch |
TYPICAL PERFOR A CE CH. ARA TERISTICS. Sample-and-Hold Acquisition. Input Channel Leakage Current. Noise Error
Modelllinie für dieses Datenblatt
Textversion des Dokuments
LTC1283
W U TYPICAL PERFOR A CE CH C ARA TERISTICS Sample-and-Hold Acquisition Input Channel Leakage Current Noise Error Time vs Source Resistance vs Temperature vs Reference Voltage
10 1000 1.2 9 VCC = 3V V V CC = 3V CC = 3V 8 VREF = 2.5V V GUARANTEED ACLK = 500kHz REF = 2.5V μs) 7 T 1.0 A = 25°C 100 6 0V TO 2.5V INPUT STEP 5 + 0.8 RSOURCE 4 10 V + IN LTC1283 NOISE = 200μVP-P ON 0.6 3 CHANNEL – 1 0.4 2 OFF CHANNEL 0.1 0.2 PEAK-TO-PEAK NOISE ERROR (LSB ) S&H ACQUISITION TIME TO 0.1% ( INPUT CHANNEL LEAKAGE CURRENT (nA) 1 0.01 0 0.1 1 10 –50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 R AMBIENT TEMPERATURE (°C) SOURCE (kΩ) REFERENCE VOLTAGE (V) LTC1283 • G13 LTC1283 • G14 LTC1283 • G15
U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION
1-8 CH0-CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND. 9 COM Common The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and is usually tied to the analog ground plane. 10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane. 11 AGND Analog Ground AGND should be tied directly to the analog ground plane. 12 V – Negative Supply Tie V – to most negative potential in the circuit. (Ground in single supply applications.) 13, 14 REF –, REF + Reference Inputs The reference inputs must be kept free of noise with respect to AGND. 15 CS Chip Select Input A logic low on this input enables data transfer. 16 DOUT Digital Data Output The A/D conversion result is shifted out of this output. 17 DIN Data Input The A/D configuration word is shifted into this input. 18 SCLK Shift Clock This clock synchronizes the serial data transfer. 19 ACLK A/D Conversion Clock This clock controls the A/D conversion process. 20 VCC Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
W BLOCK I D AGRA
18 20 SCLK VCC INPUT 17 OUTPUT 16 D SHIFT SHIFT D IN OUT REGISTER REGISTER 1 CH0 SAMPLE- 2 CH1 AND- 3 HOLD CH2 COMP 4 CH3 ANALOG 5 10-BIT INPUT MUX CH4 SAR 6 CH5 10-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM 19 ACLK CONTROL 15 10 11 12 13 14 AND CS TIMING DGND AGND V– REF– REF+ LTC1283 BD 1283fb 6
W U TYPICAL PERFOR A CE CH C ARA TERISTICS Sample-and-Hold Acquisition Input Channel Leakage Current Noise Error Time vs Source Resistance vs Temperature vs Reference Voltage
10 1000 1.2 9 VCC = 3V V V CC = 3V CC = 3V 8 VREF = 2.5V V GUARANTEED ACLK = 500kHz REF = 2.5V μs) 7 T 1.0 A = 25°C 100 6 0V TO 2.5V INPUT STEP 5 + 0.8 RSOURCE 4 10 V + IN LTC1283 NOISE = 200μVP-P ON 0.6 3 CHANNEL – 1 0.4 2 OFF CHANNEL 0.1 0.2 PEAK-TO-PEAK NOISE ERROR (LSB ) S&H ACQUISITION TIME TO 0.1% ( INPUT CHANNEL LEAKAGE CURRENT (nA) 1 0.01 0 0.1 1 10 –50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 R AMBIENT TEMPERATURE (°C) SOURCE (kΩ) REFERENCE VOLTAGE (V) LTC1283 • G13 LTC1283 • G14 LTC1283 • G15
U U U PI FU CTIO S # PIN FUNCTION DESCRIPTION
1-8 CH0-CH7 Analog Inputs The analog inputs must be free of noise with respect to AGND. 9 COM Common The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and is usually tied to the analog ground plane. 10 DGND Digital Ground This is the ground for the internal logic. Tie to the ground plane. 11 AGND Analog Ground AGND should be tied directly to the analog ground plane. 12 V – Negative Supply Tie V – to most negative potential in the circuit. (Ground in single supply applications.) 13, 14 REF –, REF + Reference Inputs The reference inputs must be kept free of noise with respect to AGND. 15 CS Chip Select Input A logic low on this input enables data transfer. 16 DOUT Digital Data Output The A/D conversion result is shifted out of this output. 17 DIN Data Input The A/D configuration word is shifted into this input. 18 SCLK Shift Clock This clock synchronizes the serial data transfer. 19 ACLK A/D Conversion Clock This clock controls the A/D conversion process. 20 VCC Positive Supply This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.
W BLOCK I D AGRA
18 20 SCLK VCC INPUT 17 OUTPUT 16 D SHIFT SHIFT D IN OUT REGISTER REGISTER 1 CH0 SAMPLE- 2 CH1 AND- 3 HOLD CH2 COMP 4 CH3 ANALOG 5 10-BIT INPUT MUX CH4 SAR 6 CH5 10-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM 19 ACLK CONTROL 15 10 11 12 13 14 AND CS TIMING DGND AGND V– REF– REF+ LTC1283 BD 1283fb 6