MCP6H91/2/4Note: Unless otherwise indicated, T A = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 60 pF. 0110-100100PSRR+CMRR-20090-30080-400oltage (μV)T = +125°CAT = +85°C70PSRR--500AT = +25°CA-600T = -40°C60AOffset V-70050-800CMRR, PSRR (dB)40Input-900Representative Part30Representative Part-100020012345678910 11 1210100100010 100 1k10000100000 100000010k 100k 1MPower Supply Voltage (V)Frequency (Hz)FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: CMRR, PSRR vs. Power Supply Voltage. Frequency. 1,000130120PSRR110Density10010090oltage V80(nV/√Hz)CMRR @ V= 12VDD1070@ V= 5VDD60@ V= 3.5VCMRR, PSRR (dB)DD50Input Noise4011 10 100 1k10k 100k 1M-50-250255075100125Frequency (Hz)Ambient Temperature (°C)FIGURE 2-8: Input Noise Voltage Density FIGURE 2-11: CMRR, PSRR vs. Ambient vs. Frequency. Temperature. 201000010n18V= 12 VDD1610001nDensity14Input Bias Current12100100poltage10Offset CurrentsV(A)8(nV/√Hz)10and10p6f = 10 kHz4V= 12 VDD11p2Input NoiseInput Offset Current0Input Bias0.10.1p-113579115253545556575859510511125Common Mode Input Voltage (V)Ambient Temperature (°C)FIGURE 2-9: Input Noise Voltage Density FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage. vs. Ambient Temperature. DS25138B-page 8 2012 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-10: CMRR, PSRR vs. Frequency. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-13: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-14: Quiescent Current vs. Ambient Temperature. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6H92 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Output Voltage Swing vs. Frequency. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Output Current. FIGURE 2-27: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-30: Slew Rate vs. Ambient Temperature. FIGURE 2-31: Slew Rate vs. Ambient Temperature. FIGURE 2-32: Small Signal Non-Inverting Pulse Response. FIGURE 2-33: Small Signal Inverting Pulse Response. FIGURE 2-34: Large Signal Non-Inverting Pulse Response. FIGURE 2-35: Large Signal Inverting Pulse Response. FIGURE 2-36: The MCP6H91/2/4 Shows No Phase Reversal. FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps 4.6 PCB Surface Leakage FIGURE 4-6: Unused Op Amps. FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: High Side Current Sensing Using Difference Amplifier. FIGURE 4-9: Active Full-Wave Rectifier. FIGURE 4-10: Non-Inverting Integrator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service