MCP6H91/2/4Note: Unless otherwise indicated, T A = +25°C, VDD = +3.5V to +12V, VSS = GND, VCM = VDD/2 - 1.4V, VOUT VDD/2, VL = VDD/2, RL = 10 kto VL and CL = 60 pF. 1307060120Current5011040100Circuit(mA) 3090T = +125°CASeparation (dB)20T = +85°CAChannel to ChannelT = +25°CA80Input Referred10T = -40°CAOutput Short700100 1k 10k 100k 1M012345678910 11 12Frequency (Hz)Power Supply Voltage (V)FIGURE 2-19: Channel-to-Channel FIGURE 2-22: Output Short Circuit Current Separation vs. Frequency (MCP6H92 only). vs. Power Supply Voltage. 14180100)160-P12Gain BandwGain Band idth ProductPP(MHz)140V= 12V10DD120ing (V 10V= 5VDD8100SwPhase Margin806V= 3.5VDDidth Product60oltage14402V= 3.5VDD20Output V00Gain Bandw0.1-50-2502550751001251000010000010k 100k1000000100000001M 10MAmbient Temperature (°C)Frequency (Hz)FIGURE 2-20: Gain Bandwidth Product, FIGURE 2-23: Output Voltage Swing vs. Phase Margin vs. Ambient Temperature. Frequency. 18180100016160(mV)V= 12VDD(MHz)14140Gain Bandwidth Product1001212010100Phase MarginHeadroom10V- VDDOH880idth Product660oltage1440V= 12VV- VSSOL2DD2000Output VGain Bandw0.1-50-2502550751001250.010.1110100Ambient Temperature (°C)Output Current (mA)FIGURE 2-21: Gain Bandwidth Product, FIGURE 2-24: Output Voltage Headroom Phase Margin vs. Ambient Temperature. vs. Output Current. DS25138B-page 10 2012 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings 1.2 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Offset Voltage vs. Power Supply Voltage. FIGURE 2-8: Input Noise Voltage Density vs. Frequency. FIGURE 2-9: Input Noise Voltage Density vs. Common Mode Input Voltage. FIGURE 2-10: CMRR, PSRR vs. Frequency. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-13: Input Bias Current vs. Common Mode Input Voltage. FIGURE 2-14: Quiescent Current vs. Ambient Temperature. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. FIGURE 2-19: Channel-to-Channel Separation vs. Frequency (MCP6H92 only). FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-22: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-23: Output Voltage Swing vs. Frequency. FIGURE 2-24: Output Voltage Headroom vs. Output Current. FIGURE 2-25: Output Voltage Headroom vs. Output Current. FIGURE 2-26: Output Voltage Headroom vs. Output Current. FIGURE 2-27: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-28: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-29: Output Voltage Headroom vs. Ambient Temperature. FIGURE 2-30: Slew Rate vs. Ambient Temperature. FIGURE 2-31: Slew Rate vs. Ambient Temperature. FIGURE 2-32: Small Signal Non-Inverting Pulse Response. FIGURE 2-33: Small Signal Inverting Pulse Response. FIGURE 2-34: Large Signal Non-Inverting Pulse Response. FIGURE 2-35: Large Signal Inverting Pulse Response. FIGURE 2-36: The MCP6H91/2/4 Shows No Phase Reversal. FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output Resistor, RISO Stabilizes Large Capacitive Loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps 4.6 PCB Surface Leakage FIGURE 4-6: Unused Op Amps. FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: High Side Current Sensing Using Difference Amplifier. FIGURE 4-9: Active Full-Wave Rectifier. FIGURE 4-10: Non-Inverting Integrator. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 MAPS (Microchip Advanced Part Selector) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Trademarks Worldwide Sales and Service