Datasheet MCP6291, MCP6291R, MCP6292, MCP6293, MCP6294, MCP6295 (Microchip) - 8

MCP6291/1R/2/3/4/5 TYPICAL PERFORMANCE CURVES (CONTINUED) Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +2.4V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, and CS is tied low.
1,000 11 y y 10 it sit 9 ns en 8 f = 10 kHz 100 e De e D ) 7 VDD = 5.0V tag Hz Hz) 6 ltag
√ √
5 V/ V/ e Vol e Vo (n (n 4 10 is is o 3 No t N 2 u 1 Input Inp 1 0
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
0.1 1 10 100 1k 10k 100k 1M 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Frequency (Hz) Common Mode Input Voltage (V) FIGURE 2-19:
Input Noise Voltage Density
FIGURE 2-22:
Input Noise Voltage Density vs. Frequency. vs. Common Mode Input Voltage at 10 kHz.
35 140 30 ent el 25 n 130 B) it Curr an h d ( 20 n rcu ) -C A o ti 120 Ci 15 (m l-to ra ne 10 TA = +125°C epa Short an T S A = +85°C h 110 ut C 5 TA = +25°C upt TA = -40°C O 0 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 10 100 Power Supply Voltage (V) Frequency (kHz) FIGURE 2-20:
Output Short Circuit Current
FIGURE 2-23:
Channel-to-Channel vs. Power Supply Voltage. Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only).
1.2 1.6 Op-Amp shuts off here V Op Amp shuts off V DD = 2.4V DD = 5.5V 1.4 Op Amp turns on 1.0 Op-Amp turns on here t t Hysteresis n ) 1.2 0.8 rren u 1.0 t C 0.6 Hysteresis 0.8 ent Curre en /Amplifier /Amplifier) 0.6 CS swept CS swept 0.4 iesc (mA high to low low to high CS swept CS swept (mA Quiesc high to low low to high 0.4 Qu 0.2 0.2 0.0 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Chip Select Voltage (V) FIGURE 2-21:
Quiescent Current vs.
FIGURE 2-24:
Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). (MCP6293 and MCP6295 only). DS21812E-page 8 © 2007 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics FIGURE 1-1: Timing Diagram for the Chip Select (CS) pin on the MCP6293 and MCP6295. 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Bias Current at TA = +85 ˚C. FIGURE 2-3: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.4V. FIGURE 2-4: Input Offset Voltage Drift. FIGURE 2-5: Input Bias Current at TA = +125 ˚C. FIGURE 2-6: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Output Voltage. FIGURE 2-8: CMRR, PSRR vs. Frequency. FIGURE 2-9: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +85˚C. FIGURE 2-10: Input Bias, Input Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Input Bias, Offset Currents vs. Common Mode Input Voltage at TA = +125˚C. FIGURE 2-13: Quiescent Current vs. Power Supply Voltage. FIGURE 2-14: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Input Noise Voltage Density vs. Frequency. FIGURE 2-20: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-21: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-22: Input Noise Voltage Density vs. Common Mode Input Voltage at 10 kHz. FIGURE 2-23: Channel-to-Channel Separation vs. Frequency (MCP6292, MCP6294 and MCP6295 only). FIGURE 2-24: Quiescent Current vs. Chip Select (CS) Voltage at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-25: Large-Signal Non-inverting Pulse Response. FIGURE 2-26: Small-Signal Non-inverting Pulse Response. FIGURE 2-27: Chip Select (CS) to Amplifier Output Response Time at VDD = 2.4V (MCP6293 and MCP6295 only). FIGURE 2-28: Large-Signal Inverting Pulse Response. FIGURE 2-29: Small-Signal Inverting Pulse Response. FIGURE 2-30: Chip Select (CS) to Amplifier Output Response Time at VDD = 5.5V (MCP6293 and MCP6295 only). FIGURE 2-31: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-32: The MCP6291/1R/2/3/4/5 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 MCP6295’s VOUTA/VINB+ Pin 3.4 Chip Select Digital Input 3.5 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO Values for Capacitive Loads. 4.4 MCP629X Chip Select 4.5 Cascaded Dual Op Amps (MCP6295) FIGURE 4-5: Cascaded Gain Amplifier. 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-8: Multiple Feedback Low- Pass Filter. FIGURE 4-9: Photodiode Amplifier. FIGURE 4-10: Isolating the Load with a Buffer. FIGURE 4-11: Cascaded Gain Circuit Configuration. FIGURE 4-12: Difference Amplifier Circuit. FIGURE 4-13: Buffered Non-inverting Integrator with Chip Select. FIGURE 4-14: Integrator Circuit with Active Compensation. FIGURE 4-15: Second-Order Multiple Feedback Low-Pass Filter with an Extra Pole- Zero Pair. FIGURE 4-16: Second-Order Sallen-Key Low-Pass Filter with an Extra Pole-Zero Pair and Chip Select. FIGURE 4-17: Capacitorless Second-Order Low-Pass Filter with Chip Select. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Simulator Tool 5.4 MAPS (Microchip Advanced Part Selector) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information