Datasheet MCP6231, MCP6231R, MCP6231U, MCP6232, MCP62314 (Microchip) - 6
Hersteller | Microchip |
Beschreibung | The Microchip Technology MCP6231/1R/1U/2/4 Operational Amplifier family has a 300 kHz gain bandwidth product and 65° (typical) phase margin |
Seiten / Seite | 40 / 6 — MCP6231/1R/1U/2/4. Note:. 1,000. 20% 18% 628 Samples. 16%. CM = VSS. 14%. … |
Dateiformat / Größe | PDF / 843 Kb |
Dokumentensprache | Englisch |
MCP6231/1R/1U/2/4. Note:. 1,000. 20% 18% 628 Samples. 16%. CM = VSS. 14%. A = -40°C to +125°C. age Density. 12%. Hz). 100. Occurrences 10%. V (n
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Textversion des Dokuments
MCP6231/1R/1U/2/4 Note:
Unless otherwise indicated, T ≈ A = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
1,000 20% 18% 628 Samples V 16% CM = VSS T 14% A = -40°C to +125°C age Density 12% lt Hz) o /
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100 Occurrences 10% V (n 8% 6% Noise V 4% rcentage of 2% e Input P 10 0% 2 0
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k -1 -1 -8 -6 -4 -2 0 2 4 6 8 10 12
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Frequency (H
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z)
4 5
Input Offset Voltage Drift (µV/°C) FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift. vs. Frequency.
550 100 ) V VCM = VSS V DD = 1.8V T 50 A = -40°C V) µ e (µ 450 TA = +25°C 0 e ( ag T lt A = +85°C ag -50 TA = +125°C Vo 350 -100 et fs -150 VDD = 5.5V 250 t Of Offset Volt -200 u V p DD = 1.8V In -250 Input 150 -300 .4 .2 0 2 4 6 8 0 2 4 6 8 0 2 -0 -0 0. 0. 0. 0. 0. 1. 1. 1. 1. 1. 2. 2. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) Output Voltage (V) FIGURE 2-8:
Input Offset Voltage vs.
FIGURE 2-11:
Input Offset Voltage vs. Common Mode Input Voltage at V Output Voltage. DD = 1.8V.
200 30 +I ) V 25 SC 150 DD = 5.5 V 20 100 TA = +125°C 15 Current T 10 50 A = +85°C T ltage (µV ) 5 A = +125°C o TA = +25°C A TA = +85°C 0 T Circuit 0 A = -40°C (m -5 TA = +25°C -50 hort- -10 TA = -40°C -100 S -15 -20 -150 Input Offset V -25 -ISC -200 Output -30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Common Mode Input Voltage (V) Power Supply Voltage (V) FIGURE 2-9:
Input Offset Voltage vs.
FIGURE 2-12:
Output Short-Circuit Current Common Mode Input Voltage at V vs. Ambient Temperature. DD = 5.5V. DS21881E-page 6 © 2009 Microchip Technology Inc. Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: PSRR, CMRR vs. Frequency. FIGURE 2-3: Input Bias Current at +85°C. FIGURE 2-4: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-5: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-6: Input Bias Current at +125°C. FIGURE 2-7: Input Noise Voltage Density vs. Frequency. FIGURE 2-8: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-9: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-10: Input Offset Voltage Drift. FIGURE 2-11: Input Offset Voltage vs. Output Voltage. FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature. FIGURE 2-13: Slew Rate vs. Ambient Temperature. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-20: The MCP6231/1R/1U/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply (VSS and VDD) 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: The MCP6231/1R/1U/2/4 Show No Phase Reversal. FIGURE 4-2: Simplified Analog Input ESD Structures. FIGURE 4-3: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-4: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-5: Recommended RISO Values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-6: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-7: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-8: Summing Amplifier Circuit. FIGURE 4-9: Effect of Parasitic Capacitance at the Input. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information