Datasheet MCP6L71, MCP6L71R, MCP6L72, MCP6L74 (Microchip) - 5

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MCP6L71/1R/2/4 1.3 Test Circuits
C The circuit used for most DC and AC tests is shown in F 6.8 pF Figure 1-1. This circuit can independently set VCM and VOUT; see Equation 1-1. Note that VCM is not the circuit’s common mode voltage ((V R P + VM)/2), and that G RF VOST includes VOS plus the effects (on the input offset 100 kΩ 100 kΩ error, V V V OST) of temperature, CMRR, PSRR and AOL. P DD/2 VDD V
EQUATION 1-1:
IN+ C C B1 B2 G = R ⁄ R DM F G
MCP6L7X
100 nF 1 µF V = (V + V ⁄ 2) ⁄ 2 CM P DD V = V – V V OST IN– IN+ IN– V = (V ⁄ 2) + (V – V ) + V (1 + G ) OUT DD P M OST DM V V M OUT Where: R R C G RF L L 100 kΩ 100 kΩ 10 kΩ 60 pF GDM = Differential Mode Gain (V/V) VCM = Op Amp’s Common Mode (V) Input Voltage CF VL 6.8 pF VOST = Op Amp’s Total Input Offset (mV) Voltage
FIGURE 1-1:
AC and DC Test Circuit for Most Specifications. © 2009 Microchip Technology Inc. DS22145A-page 5 Document Outline 1.0 Electrical Characteristics 1.1 Absolute Maximum Ratings † 1.2 Specifications TABLE 1-1: DC Electrical Specifications (Continued) TABLE 1-2: AC Electrical Specifications TABLE 1-3: Temperature Specifications 1.3 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 2.0V. FIGURE 2-2: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-3: Input Offset Voltage vs. Output Voltage. FIGURE 2-4: Input Common Mode Range Voltage vs. Ambient Temperature. FIGURE 2-5: CMRR, PSRR vs. Temperature. FIGURE 2-6: CMRR, PSRR vs. Frequency. FIGURE 2-7: Input Current vs. Input Voltage. FIGURE 2-8: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-9: Input Noise Voltage Density vs. Frequency. FIGURE 2-10: The MCP6L71/1R/2/4 Show No Phase Reversal. FIGURE 2-11: Quiescent Current vs. Supply Voltage. FIGURE 2-12: Output Short Circuit Current vs. Supply Voltage. FIGURE 2-13: Ratio of Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-14: Large Signal Non-inverting Pulse Response. FIGURE 2-15: Small Signal Non-inverting Pulse Response. FIGURE 2-16: Slew Rate vs. Ambient Temperature. FIGURE 2-17: Maximum Output Voltage Swing vs. Frequency. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table for Single Op Amps TABLE 3-2: Pin Function Table for Dual and Quad Op Amps 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-2: Output Resistor, RISO Stabilizes Large Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Amplifiers FIGURE 4-3: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-4: Example Guard Ring Layout. 4.7 Application Circuits FIGURE 4-5: Inverting Integrator. 5.0 Design Tools 5.1 FilterLab® Software 5.2 MAPS (Microchip Advanced Part Selector) 5.3 Analog Demonstration and Evaluation Boards 5.4 Application Notes 6.0 Packaging Information 6.1 Package Marking Information