Datasheet LT1713, LT1714 (Analog Devices) - 4

LT1713/LT1714
ELECTRICAL CHARACTERISTICS The
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denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25
°
C. V+ = 5V, V– = – 5V, VCM = 0V, VLATCH = 0.8V, CLOAD = 10pF, VOVERDRIVE = 20mV, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Input Voltage Range ● – 5.1 5.1 V CMRR Common Mode Rejection Ratio – 5V ≤ VCM ≤ 5V 62 70 dB ● 60 dB PSRR+ Positive Power Supply Rejection Ratio 2.4V ≤ V+ ≤ 7V, VCM = – 5V 68 80 dB ● 65 dB PSRR– Negative Power Supply Rejection Ratio – 7V ≤ V– ≤ 0V, VCM = 5V 65 80 dB ● 60 dB AV Small-Signal Voltage Gain (Note 10) 1V ≤ VOUT ≤ 4V, RL = ∞ 1.5 3 V/mV VOH Output Voltage Swing HIGH (Note 8) IOUT = 1mA, VOVERDRIVE = 50mV ● 4.5 4.8 V IOUT = 10mA, VOVERDRIVE = 50mV ● 4.3 4.6 V VOL Output Voltage Swing LOW (Note 8) IOUT = – 1mA, VOVERDRIVE = 50mV ● 0.20 0.4 V IOUT = – 10mA, VOVERDRIVE = 50mV ● 0.35 0.5 V I+ Positive Supply Current (Per Comparator) VOVERDRIVE = 1V 5.5 7.5 mA ● 9.0 mA I– Negative Supply Current (Per Comparator) VOVERDRIVE = 1V 3.5 4.5 mA ● 5.0 mA VIH Latch Pin High Input Voltage ● 2.4 V VIL Latch Pin Low Input Voltage ● 0.8 V IIL Latch Pin Current VLATCH = V+ ● 10 µA tPD Propagation Delay (Note 6) ∆VIN = 100mV, VOVERDRIVE = 20mV 7 10 ns ∆VIN = 100mV, VOVERDRIVE = 20mV ● 12 ns ∆VIN = 100mV, VOVERDRIVE = 5mV 8.5 ns ∆tPD Differential Propagation Delay (Note 6) ∆VIN = 100mV, VOVERDRIVE = 20mV 0.5 3 ns tr Output Rise Time 10% to 90% 4 ns tf Output Fall Time 90% to 10% 4 ns tLPD Latch Propagation Delay (Note 7) 8 ns tSU Latch Setup Time (Note 7) 1.5 ns tH Latch Hold Time (Note 7) 0 ns tDPW Minimum Latch Disable Pulse Width (Note 7) 8 ns fMAX Maximum Toggle Frequency VIN = 100mVP-P Sine Wave 65 MHz tJITTER Output Timing Jitter VIN = 630mVP-P (0dBm) Sine Wave, f = 30MHz 15 psRMS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 6:
Propagation delay (tPD) is measured with the overdrive added to of a device may be impaired. the actual VOS. Differential propagation delay is defined as: + –
Note 2:
The LT1713C/LT1714C are guaranteed to meet specified ∆tPD = tPD – tPD . Load capacitance is 10pF. Due to test system performance from 0°C to 70°C. They are designed, characterized and requirements, the LT1713/LT1714 propagation delay is specified with a expected to meet specified performance from – 40°C to 85°C but are not 1kΩ load to ground for ±5V supplies, or to mid-supply for 2.7V or 5V tested or QA sampled at these temperatures. The LT1713I/LT1714I are single supplies. guaranteed to meet specified performance from – 40°C to 85°C.
Note 7:
Latch propagation delay (tLPD) is the delay time for the output to
Note 3:
The negative supply should not be greater than the ground pin respond when the latch pin is deasserted. Latch setup time (tSU) is the voltages and the maximum voltage across the positive and negative interval in which the input signal must remain stable prior to asserting the supplies should not be greater than 12V. latch signal. Latch hold time (tH) is the interval after the latch is asserted in
Note 4:
Input offset voltage (V which the input signal must remain stable. Latch disable pulse width OS) is defined as the average of the two voltages measured by forcing first one output, then the other to V+/2. (tDPW) is the width of the negative pulse on the latch enable pin that latches in new data on the data inputs.
Note 5:
Input bias current (IB) is defined as the average of the two input currents. 4