Datasheet LTC2387-18 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 18-Bit, 15Msps SAR ADC |
| Seiten / Seite | 24 / 9 — pin FuncTions VDD (Pins 11, 12):. TWOLANES (Pin 25):. PD (Pin 13):. … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
pin FuncTions VDD (Pins 11, 12):. TWOLANES (Pin 25):. PD (Pin 13):. CNV–/CNV+ (Pins 27/28):. TESTPAT (Pin 14):
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LTC2387-18
pin FuncTions VDD (Pins 11, 12):
5V Analog Power Supply. The range
TWOLANES (Pin 25):
Digital input that enables two-lane of VDD is 4.75V to 5.25V. The two pins should be shorted output mode. When TWOLANES is high (two-lane output together and bypassed to GND with 0.1μF and 10μF ce- mode), the ADC outputs two bits at a time on DA–/DA+ ramic capacitors. and DB–/DB+. When TWOLANES is low (one-lane output
PD (Pin 13):
Digital input that enables power-down mode. mode), the ADC outputs one bit at a time on DA–/DA+, and When PD is low, the LTC2387 enters power-down mode, DB–/DB+ are disabled. Logic levels are determined by VDDL. and all circuitry (including the LVDS interface) is shut
CNV–/CNV+ (Pins 27/28):
Conversion Start LVDS Input. down. When PD is high, the part operates normally. Logic A rising edge on CNV+ puts the internal sample-and-hold levels are determined by OVDD. into the hold mode and starts a conversion cycle. CNV+
TESTPAT (Pin 14):
Digital input that forces the LVDS data can also be driven with a 2.5V CMOS signal if CNV– is outputs to be a test pattern. When TESTPAT is high, the tied to GND. digital outputs are a test pattern. When TESTPAT is low,
VDDL (Pins 30, 31):
2.5V Analog Power Supply. The the digital outputs are the ADC conversion result. Logic range of VDDL is 2.375V to 2.625V. The two pins should levels are determined by OVDD. be shorted together and bypassed to GND with 0.1μF and
DB–/DB+, DA–/DA+ (Pins 15/16, 17/18):
Serial LVDS 10μF ceramic capacitors. Data Outputs. In one-lane output mode, DB–/DB+ are not
VCM (Pin 32):
Common Mode Output. VCM, nominally used and their LVDS driver is disabled to reduce power 2.048V, can be used to set the common mode of the ana- consumption. log inputs. Bypass to GND with a 0.1μF ceramic capacitor
DCO–/DCO+ (Pins 19/20):
LVDS Data Clock Output. This close to the pin. If VCM is not used, the bypass capacitor is an echoed version of CLK–/CLK+ that can be used to is not necessary as long as the parasitic capacitance on latch the data outputs. the VCM pin is under 10pF.
OV Exposed Pad (Pin 33):
The exposed pad on the bottom
DD (Pin 22):
2.5V Output Power Supply. The range of OV of the package. Connect to the ground plane of the PCB DD is 2.375V to 2.625V. Bypass to GND with a 0.1μF ceramic capacitor. using multiple vias.
CLK–/CLK+ (Pins 23/24):
LVDS Clock Input. This is an externally applied clock that serially shifts out the conver- sion result. 238718fa For more information www.linear.com/LTC2387-18 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts
pin FuncTions VDD (Pins 11, 12):
5V Analog Power Supply. The range
TWOLANES (Pin 25):
Digital input that enables two-lane of VDD is 4.75V to 5.25V. The two pins should be shorted output mode. When TWOLANES is high (two-lane output together and bypassed to GND with 0.1μF and 10μF ce- mode), the ADC outputs two bits at a time on DA–/DA+ ramic capacitors. and DB–/DB+. When TWOLANES is low (one-lane output
PD (Pin 13):
Digital input that enables power-down mode. mode), the ADC outputs one bit at a time on DA–/DA+, and When PD is low, the LTC2387 enters power-down mode, DB–/DB+ are disabled. Logic levels are determined by VDDL. and all circuitry (including the LVDS interface) is shut
CNV–/CNV+ (Pins 27/28):
Conversion Start LVDS Input. down. When PD is high, the part operates normally. Logic A rising edge on CNV+ puts the internal sample-and-hold levels are determined by OVDD. into the hold mode and starts a conversion cycle. CNV+
TESTPAT (Pin 14):
Digital input that forces the LVDS data can also be driven with a 2.5V CMOS signal if CNV– is outputs to be a test pattern. When TESTPAT is high, the tied to GND. digital outputs are a test pattern. When TESTPAT is low,
VDDL (Pins 30, 31):
2.5V Analog Power Supply. The the digital outputs are the ADC conversion result. Logic range of VDDL is 2.375V to 2.625V. The two pins should levels are determined by OVDD. be shorted together and bypassed to GND with 0.1μF and
DB–/DB+, DA–/DA+ (Pins 15/16, 17/18):
Serial LVDS 10μF ceramic capacitors. Data Outputs. In one-lane output mode, DB–/DB+ are not
VCM (Pin 32):
Common Mode Output. VCM, nominally used and their LVDS driver is disabled to reduce power 2.048V, can be used to set the common mode of the ana- consumption. log inputs. Bypass to GND with a 0.1μF ceramic capacitor
DCO–/DCO+ (Pins 19/20):
LVDS Data Clock Output. This close to the pin. If VCM is not used, the bypass capacitor is an echoed version of CLK–/CLK+ that can be used to is not necessary as long as the parasitic capacitance on latch the data outputs. the VCM pin is under 10pF.
OV Exposed Pad (Pin 33):
The exposed pad on the bottom
DD (Pin 22):
2.5V Output Power Supply. The range of OV of the package. Connect to the ground plane of the PCB DD is 2.375V to 2.625V. Bypass to GND with a 0.1μF ceramic capacitor. using multiple vias.
CLK–/CLK+ (Pins 23/24):
LVDS Clock Input. This is an externally applied clock that serially shifts out the conver- sion result. 238718fa For more information www.linear.com/LTC2387-18 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Pin Configuration Converter Characteristics Dynamic Accuracy Internal Reference Characteristics Reference Buffer Characteristics Digital Inputs and Digital Outputs Power Requirements ADC Timing Characteristics Typical Performance Characteristics Pin Functions Functional Block Diagram Timing Diagram Applications Information Package Description Typical Application Related Parts