Datasheet AD7091 (Analog Devices) - 10

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AD7091 Data Sheet THEORY OF OPERATION CIRCUIT INFORMATION
When the ADC starts a conversion, SW2 opens and SW1 moves The AD7091 is a 12-bit successive approximation register to Position B, causing the comparator to become unbalanced (see analog-to-digital converter (SAR ADC) that offers ultralow Figure 16). The control logic and the charge redistribution DAC power consumption (typically 367 μA at 3 V and 1 MSPS) while are used to add and subtract fixed amounts of charge from the achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). sampling capacitor to bring the comparator back into a balanced The part operates from a single power supply in the range of condition. When the comparator is rebalanced, the conversion 2.09 V to 5.25 V. is complete. The control logic generates the ADC output code. Figure 17 shows the ADC transfer function. The AD7091 provides an on-chip track-and-hold amplifier and an analog-to-digital converter (ADC) with a serial interface
CHARGE
housed in a tiny 8-lead LFCSP package. This package offers
REDISTRIBUTION DAC
considerable space-saving advantages compared with alternative
SAMPLING
solutions. The serial clock input accesses data from the part. The
CAPACITOR A VIN
clock for the SAR ADC is generated internally.
SW1 CONTROL SW2 LOGIC B CONVERSION
The analog input range is 0 V to V
PHASE
DD. An external reference is
COMPARATOR
16 -0 not required for the ADC, nor is there a reference on chip. The
GND
494
LDO/2
10 reference voltage for the AD7091 is derived from the power Figure 16. ADC Conversion Phase supply and, thus, provides the widest dynamic input range of 0 V to V
ADC TRANSFER FUNCTION
DD. The AD7091 also features a power-down option to save power The output coding of the AD7091 is straight binary. The designed between conversions. The power-down feature is implemented code transitions occur midway between successive integer LSB using the standard serial interface, as described in the Modes of values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the Operation section. AD7091 is VDD/4096. The ideal transfer characteristic for the AD7091 is shown in Figure 17.
CONVERTER OPERATION
The AD7091 is a SAR ADC based around a charge redistribu-
111 ... 111 111 ... 110
tion DAC. Figure 15 and Figure 16 show simplified schematics of the ADC.
DE 111 ... 000 1LSB = VDD /4096
Figure 15 shows the ADC during its acquisition phase; SW2 is
011 ... 111 DC CO A
closed and SW1 is in Position A. The comparator is held in a balanced condition, and the sampling capacitor acquires the
000 ... 010 000 ... 001
signal on V
000 ... 000
IN. 17 0
1LSB 0V VDD – 1LSB
4- 49
ANALOG INPUT
10
CHARGE
Figure 17. AD7091 Transfer Characteristic
REDISTRIBUTION DAC SAMPLING CAPACITOR A VIN CONTROL SW1 LOGIC B ACQUISITION PHASE SW2 COMPARATOR GND
015
LDO/2
10494- Figure 15. ADC Acquisition Phase Rev. B | Page 10 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT MODES OF OPERATION Normal Mode Power-Down Mode POWER CONSUMPTION Power Consumption in Normal Mode Power Consumption Using a Combination of Normal Mode and Power-Down Mode MULTIPLEXER APPLICATIONS SERIAL INTERFACE BUSY INDICATOR ENABLED BUSY INDICATOR DISABLED SOFTWARE RESET INTERFACING WITH AN 8-/16-BIT SPI BUS OUTLINE DIMENSIONS ORDERING GUIDE