Datasheet Complete ATmega328PB (Atmel) - 8

link to page 376 link to page 380 link to page 380 link to page 381 link to page 382 link to page 383 link to page 385 link to page 386 link to page 389 link to page 389 link to page 392 link to page 394 link to page 394 link to page 395 link to page 398 link to page 400 link to page 402 link to page 404 link to page 406 link to page 409 link to page 411 link to page 413 link to page 417 link to page 421 link to page 421 link to page 422 link to page 423 link to page 423 link to page 423 link to page 423 link to page 424 34.2. DC Characteristics..376 34.3. Speed Grades.. 380 34.4. Clock Characteristics..380 34.5. System and Reset Characteristics... 381 34.6. SPI Timing Characteristics... 382 34.7. Two-wire Serial Interface Characteristics... 383 34.8. ADC Characteristics... 385 34.9. Parallel Programming Characteristics.. 386 35. Typical Characteristics...389 35.1. Active Supply Current...389 35.2. Idle Supply Current...392 35.3. ATmega328PB Supply Current of IO Modules... 394 35.4. Power-down Supply Current...394 35.5. Pin Pull-Up..395 35.6. Pin Driver Strength... 398 35.7. Pin Threshold and Hysteresis...400 35.8. BOD Threshold...402 35.9. Analog Comparator Offset..404 35.10. Internal Oscillator Speed..406 35.11. Current Consumption of Peripheral Units...409 35.12. Current Consumption in Reset and Reset Pulse Width..411 36. Register Summary...413 37. Instruction Set Summary... 417 38. Packaging Information...421 38.1. 32A... 421 38.2. 32MS1.. 422 39. Errata...423 39.1. Rev. A...423 39.2. Rev. B...423 39.3. Rev. C...423 40. Revision History...424 Atmel ATmega328PB [DATASHEET] 8 Atmel-42397C-8-bit AVR-ATmega328PB_Datasheet_Complete-10/2015 Document Outline Introduction Feature Table of Contents 1. Description 2. Configuration Summary 3. Ordering Information 4. Block Diagram 5. Pin Configurations 5.1. Pin Descriptions 5.1.1. VCC 5.1.2. GND 5.1.3. Port B (PB[7:0]) XTAL1/XTAL2/TOSC1/TOSC2 5.1.4. Port C (PC[5:0]) 5.1.5. PC6/RESET 5.1.6. Port D (PD[7:0]) 5.1.7. Port E (PE[3:0]) 5.1.8. AVCC 5.1.9. AREF 5.1.10. ADC[7:6] (TQFP and VFQFN Package Only) 6. I/O Multiplexing 7. Resources 8. Data Retention 9. About Code Examples 10. AVR CPU Core 10.1. Overview 10.2. ALU – Arithmetic Logic Unit 10.3. Status Register 10.3.1. Status Register 10.4. General Purpose Register File 10.4.1. The X-register, Y-register, and Z-register 10.5. Stack Pointer 10.5.1. SPH and SPL - Stack Pointer High and Stack Pointer Low Register 10.6. Instruction Execution Timing 10.7. Reset and Interrupt Handling 10.7.1. Interrupt Response Time 11. AVR Memories 11.1. Overview 11.2. In-System Reprogrammable Flash Program Memory 11.3. SRAM Data Memory 11.3.1. Data Memory Access Times 11.4. EEPROM Data Memory 11.4.1. EEPROM Read/Write Access 11.4.2. Preventing EEPROM Corruption 11.5. I/O Memory 11.5.1. General Purpose I/O Registers 11.6. Register Description 11.6.1. EEPROM Address Register High 11.6.2. EEPROM Address Register Low 11.6.3. EEPROM Data Register 11.6.4. EEPROM Control Register 11.6.5. GPIOR2 – General Purpose I/O Register 2 11.6.6. GPIOR1 – General Purpose I/O Register 1 11.6.7. GPIOR0 – General Purpose I/O Register 0 12. System Clock and Clock Options 12.1. Clock Systems and Their Distribution 12.1.1. CPU Clock – clkCPU 12.1.2. I/O Clock – clkI/O 12.1.3. PTC Clock - clkPTC 12.1.4. Flash Clock – clkFLASH 12.1.5. Asynchronous Timer Clock – clkASY 12.1.6. ADC Clock – clkADC 12.2. Clock Sources 12.2.1. Default Clock Source 12.2.2. Clock Startup Sequence 12.3. Low Power Crystal Oscillator 12.4. Low Frequency Crystal Oscillator 12.5. Calibrated Internal RC Oscillator 12.6. 128kHz Internal Oscillator 12.7. External Clock 12.8. Clock Output Buffer 12.9. Timer/Counter Oscillator 12.10. System Clock Prescaler 12.11. Register Description 12.11.1. Oscillator Calibration Register 12.11.2. Clock Prescaler Register 13. CFD - Clock Failure Detection mechanism 13.1. Overview 13.2. Features 13.3. Operations 13.4. Timing Diagram 13.5. Register Description 13.5.1. XOSC Failure Detection Control And Status Register 14. PM - Power Management and Sleep Modes 14.1. Sleep Modes 14.2. BOD Disable 14.3. Idle Mode 14.4. ADC Noise Reduction Mode 14.5. Power-Down Mode 14.6. Power-save Mode 14.7. Standby Mode 14.8. Extended Standby Mode 14.9. Power Reduction Register 14.10. Minimizing Power Consumption 14.10.1. Analog to Digital Converter 14.10.2. Analog Comparator 14.10.3. Brown-Out Detector 14.10.4. Internal Voltage Reference 14.10.5. Watchdog Timer 14.10.6. Port Pins 14.10.7. On-chip Debug System 14.11. Register Description 14.11.1. Sleep Mode Control Register 14.11.2. MCU Control Register 14.11.3. Power Reduction Register 0 15. SCRST - System Control and Reset 15.1. Resetting the AVR 15.2. Reset Sources 15.3. Power-on Reset 15.4. External Reset 15.5. Brown-out Detection 15.6. Watchdog System Reset 15.7. Internal Voltage Reference 15.7.1. Voltage Reference Enable Signals and Start-up Time 15.8. Watchdog Timer 15.8.1. Features 15.8.2. Overview 15.9. Register Description 15.9.1. MCU Status Register 15.9.2. WDTCSR – Watchdog Timer Control Register 16. INT- Interrupts 16.1. Interrupt Vectors in ATmega328PB 16.2. Register Description 16.2.1. Moving Interrupts Between Application and Boot Space 16.2.2. MCU Control Register 17. EXINT - External Interrupts 17.1. Pin Change Interrupt Timing 17.2. Register Description 17.2.1. External Interrupt Control Register A 17.2.2. External Interrupt Mask Register 17.2.3. External Interrupt Flag Register 17.2.4. Pin Change Interrupt Control Register 17.2.5. Pin Change Interrupt Flag Register 17.2.6. Pin Change Mask Register 3 17.2.7. Pin Change Mask Register 2 17.2.8. Pin Change Mask Register 1 17.2.9. Pin Change Mask Register 0 18. I/O-Ports 18.1. Overview 18.2. Ports as General Digital I/O 18.2.1. Configuring the Pin 18.2.2. Toggling the Pin 18.2.3. Switching Between Input and Output 18.2.4. Reading the Pin Value 18.2.5. Digital Input Enable and Sleep Modes 18.2.6. Unconnected Pins 18.3. Alternate Port Functions 18.3.1. Alternate Functions of Port B 18.3.2. Alternate Functions of Port C 18.3.3. Alternate Functions of Port D 18.3.4. Alternate Functions of Port E 18.4. Register Description 18.4.1. MCU Control Register 18.4.2. Port B Data Register 18.4.3. Port B Data Direction Register 18.4.4. Port B Input Pins Address 18.4.5. Port C Data Register 18.4.6. Port C Data Direction Register 18.4.7. Port C Input Pins Address 18.4.8. Port D Data Register 18.4.9. Port D Data Direction Register 18.4.10. Port D Input Pins Address 18.4.11. Port E Data Register 18.4.12. Port E Data Direction Register 18.4.13. Port E Input Pins Address 19. TC0 - 8-bit Timer/Counter with PWM 19.1. Features 19.2. Overview 19.2.1. Definitions 19.2.2. Registers 19.3. Timer/Counter Clock Sources 19.4. Counter Unit 19.5. Output Compare Unit 19.5.1. Force Output Compare 19.5.2. Compare Match Blocking by TCNT0 Write 19.5.3. Using the Output Compare Unit 19.6. Compare Match Output Unit 19.6.1. Compare Output Mode and Waveform Generation 19.7. Modes of Operation 19.7.1. Normal Mode 19.7.2. Clear Timer on Compare Match (CTC) Mode 19.7.3. Fast PWM Mode 19.7.4. Phase Correct PWM Mode 19.8. Timer/Counter Timing Diagrams 19.9. Register Description 19.9.1. TC0 Control Register A 19.9.2. TC0 Control Register B 19.9.3. TC0 Interrupt Mask Register 19.9.4. General Timer/Counter Control Register 19.9.5. TC0 Counter Value Register 19.9.6. TC0 Output Compare Register A 19.9.7. TC0 Output Compare Register B 19.9.8. T0 Interrupt Flag Register 20. TC - 16-bit Timer/Counter with PWM 20.1. Features 20.2. Overview 20.2.1. Definitions 20.2.2. Registers 20.3. Accessing 16-bit Registers 20.3.1. Reusing the Temporary High Byte Register 20.4. Timer/Counter Clock Sources 20.5. Counter Unit 20.6. Input Capture Unit 20.6.1. Input Capture Trigger Source 20.6.2. Noise Canceler 20.6.3. Using the Input Capture Unit 20.7. Compare Match Output Unit 20.7.1. Compare Output Mode and Waveform Generation 20.8. Output Compare Units 20.9. Modes of Operation 20.9.1. Normal Mode 20.9.2. Clear Timer on Compare Match (CTC) Mode 20.9.3. Fast PWM Mode 20.9.4. Phase Correct PWM Mode 20.9.5. Phase and Frequency Correct PWM Mode 20.10. Timer/Counter Timing Diagrams 20.11. Register Description 20.11.1. TCn Control Register A 20.11.2. TC n Control Register B 20.11.3. TC4 Control Register C 20.11.4. TCn Counter Value Low byte 20.11.5. TCn Counter High byte 20.11.6. Input Capture Register n Low byte 20.11.7. Input Capture Register n High byte 20.11.8. Output Compare Register n A Low byte 20.11.9. Output Compare Register n A High byte 20.11.10. Output Compare Register n B Low byte 20.11.11. Output Compare Register n B High byte 20.11.12. Timer/Counter 1 Interrupt Mask Register 20.11.13. Timer/Counter n Interrupt Mask Register 20.11.14. TC 1 Interrupt Flag Register 20.11.15. TCn Interrupt Flag Register 21. Timer/Counter0 and Timer/Counter1,3,4 Prescalers 21.1. Internal Clock Source 21.2. Prescaler Reset 21.3. External Clock Source 21.4. Register Description 21.4.1. General Timer/Counter Control Register 22. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation 22.1. Features 22.2. Overview 22.2.1. Definitions 22.2.2. Registers 22.3. Timer/Counter Clock Sources 22.4. Counter Unit 22.5. Output Compare Unit 22.5.1. Force Output Compare 22.5.2. Compare Match Blocking by TCNT2 Write 22.5.3. Using the Output Compare Unit 22.6. Compare Match Output Unit 22.6.1. Compare Output Mode and Waveform Generation 22.7. Modes of Operation 22.7.1. Normal Mode 22.7.2. Clear Timer on Compare Match (CTC) Mode 22.7.3. Fast PWM Mode 22.7.4. Phase Correct PWM Mode 22.8. Timer/Counter Timing Diagrams 22.9. Asynchronous Operation of Timer/Counter2 22.10. Timer/Counter Prescaler 22.11. Register Description 22.11.1. TC2 Control Register A 22.11.2. TC2 Control Register B 22.11.3. TC2 Counter Value Register 22.11.4. TC2 Output Compare Register A 22.11.5. TC2 Output Compare Register B 22.11.6. TC2 Interrupt Mask Register 22.11.7. TC2 Interrupt Flag Register 22.11.8. Asynchronous Status Register 22.11.9. General Timer/Counter Control Register 23. OCM - Output Compare Modulator 23.1. Overview 23.2. Description 23.2.1. Timing Example 24. SPI – Serial Peripheral Interface 24.1. Features 24.2. Overview 24.3. SS Pin Functionality 24.3.1. Slave Mode 24.3.2. Master Mode 24.4. Data Modes 24.5. Register Description 24.5.1. SPI Control Register 0 24.5.2. SPI Control Register 1 24.5.3. SPI Status Register 0 24.5.4. SPI Status Register 1 24.5.5. SPI Data Register 0 24.5.6. SPI Data Register 1 25. USART - Universal Synchronous Asynchronous Receiver Transceiver 25.1. Features 25.2. Overview 25.3. Clock Generation 25.3.1. Internal Clock Generation – The Baud Rate Generator 25.3.2. Double Speed Operation (U2X) 25.3.3. External Clock 25.3.4. Synchronous Clock Operation 25.4. Frame Formats 25.4.1. Parity Bit Calculation 25.5. USART Initialization 25.6. Data Transmission – The USART Transmitter 25.6.1. Sending Frames with 5 to 8 Data Bits 25.6.2. Sending Frames with 9 Data Bit 25.6.3. Transmitter Flags and Interrupts 25.6.4. Parity Generator 25.6.5. Disabling the Transmitter 25.7. Data Reception – The USART Receiver 25.7.1. Receiving Frames with 5 to 8 Data Bits 25.7.2. Receiving Frames with 9 Data Bits 25.7.3. Receive Compete Flag and Interrupt 25.7.4. Receiver Error Flags 25.7.5. Parity Checker 25.7.6. Disabling the Receiver 25.7.7. Flushing the Receive Buffer 25.8. Asynchronous Data Reception 25.8.1. Asynchronous Clock Recovery 25.8.2. Asynchronous Data Recovery 25.8.3. Asynchronous Operational Range 25.8.4. Start Frame Detection 25.9. Multi-Processor Communication Mode 25.9.1. Using MPCMn 25.10. Examples of Baud Rate Setting 25.11. Register Description 25.11.1. USART I/O Data Register n 25.11.2. USART Control and Status Register n A 25.11.3. USART Control and Status Register n B 25.11.4. USART Control and Status Register n C 25.11.5. USART Control and Status Register n D 25.11.6. USART Baud Rate n Register Low 25.11.7. USART Baud Rate n Register High 26. USARTSPI - USART in SPI Mode 26.1. Features 26.2. Overview 26.3. Clock Generation 26.4. SPI Data Modes and Timing 26.5. Frame Formats 26.5.1. USART MSPIM Initialization 26.6. Data Transfer 26.6.1. Transmitter and Receiver Flags and Interrupts 26.6.2. Disabling the Transmitter or Receiver 26.7. AVR USART MSPIM vs. AVR SPI 26.8. Register Description 27. TWI - 2-wire Serial Interface 27.1. Features 27.2. Two-Wire Serial Interface Bus Definition 27.2.1. TWI Terminology 27.2.2. Electrical Interconnection 27.3. Data Transfer and Frame Format 27.3.1. Transferring Bits 27.3.2. START and STOP Conditions 27.3.3. Address Packet Format 27.3.4. Data Packet Format 27.3.5. Combining Address and Data Packets into a Transmission 27.4. Multi-master Bus Systems, Arbitration and Synchronization 27.5. Overview of the TWI Module 27.5.1. SCL and SDA Pins 27.5.2. Bit Rate Generator Unit 27.5.3. Bus Interface Unit 27.5.4. Address Match Unit 27.5.5. Control Unit 27.6. Using the TWI 27.7. Transmission Modes 27.7.1. Master Transmitter Mode 27.7.2. Master Receiver Mode 27.7.3. Slave Transmitter Mode 27.7.4. Slave Receiver Mode 27.7.5. Miscellaneous States 27.7.6. Combining Several TWI Modes 27.8. Multi-master Systems and Arbitration 27.9. Register Description 27.9.1. TWI Bit Rate Register n 27.9.2. TWI Status Register n 27.9.3. TWI (Slave) Address Register n 27.9.4. TWI Data Register n 27.9.5. TWI Control Register n 27.9.6. TWI (Slave) Address Mask Register n 28. AC - Analog Comparator 28.1. Overview 28.2. Analog Comparator Multiplexed Input 28.3. Register Description 28.3.1. Analog Comparator Control and Status Register B 28.3.2. Analog Comparator Control and Status Register 28.3.3. Digital Input Disable Register 1 29. ADC - Analog to Digital Converter 29.1. Features 29.2. Overview 29.3. Starting a Conversion 29.4. Prescaling and Conversion Timing 29.5. Changing Channel or Reference Selection 29.5.1. ADC Input Channels 29.5.2. ADC Voltage Reference 29.6. ADC Noise Canceler 29.6.1. Analog Input Circuitry 29.6.2. Analog Noise Canceling Techniques 29.6.3. ADC Accuracy Definitions 29.7. ADC Conversion Result 29.8. Temperature Measurement 29.9. Register Description 29.9.1. ADC Multiplexer Selection Register 29.9.2. ADC Control and Status Register A 29.9.3. ADC Data Register Low (ADLAR=0) 29.9.4. ADC Data Register High (ADLAR=0) 29.9.5. ADC Data Register Low (ADLAR=1) 29.9.6. ADC Data Register High (ADLAR=1) 29.9.7. ADC Control and Status Register B 29.9.8. Digital Input Disable Register 0 30. PTC - Peripheral Touch Controller 30.1. Overview 30.2. Features 30.3. Block Diagram 30.4. Signal Description 30.5. Product Dependencies 30.5.1. I/O Lines 30.5.1.1. Mutual-capacitance Sensor Arrangement 30.5.1.2. Self-capacitance Sensor Arrangement 30.5.2. Clocks 30.6. Functional Description 31. DBG - debugWIRE On-chip Debug System 31.1. Features 31.2. Overview 31.3. Physical Interface 31.4. Software Break Points 31.5. Limitations of debugWIRE 31.6. Register Description 31.6.1. debugWire Data Register 32. Boot Loader Support – Read-While-Write Self-Programming 32.1. Features 32.2. Overview 32.3. Application and Boot Loader Flash Sections 32.3.1. Application Section 32.3.2. BLS – Boot Loader Section 32.4. Read-While-Write and No Read-While-Write Flash Sections 32.4.1. RWW – Read-While-Write Section 32.4.2. NRWW – No Read-While-Write Section 32.5. Entering the Boot Loader Program 32.6. Boot Loader Lock Bits 32.7. Addressing the Flash During Self-Programming 32.8. Self-Programming the Flash 32.8.1. Performing Page Erase by SPM 32.8.2. Filling the Temporary Buffer (Page Loading) 32.8.3. Performing a Page Write 32.8.4. Using the SPM Interrupt 32.8.5. Consideration While Updating Boot Loader Section (BLS) 32.8.6. Prevent Reading the RWW Section During Self-Programming 32.8.7. Setting the Boot Loader Lock Bits by SPM 32.8.8. EEPROM Write Prevents Writing to SPMCSR 32.8.9. Reading the Fuse and Lock Bits from Software 32.8.10. Reading the Signature Row from Software 32.8.11. Preventing Flash Corruption 32.8.12. Programming Time for Flash when Using SPM 32.8.13. Simple Assembly Code Example for a Boot Loader 32.8.14. ATmega328PB Boot Loader Parameters 32.9. Register Description 32.9.1. SPMCSR – Store Program Memory Control and Status Register 33. MEMPROG- Memory Programming 33.1. Program And Data Memory Lock Bits 33.2. Fuse Bits 33.2.1. Latching of Fuses 33.3. Signature Bytes 33.4. Calibration Byte 33.5. Serial Number 33.6. Page Size 33.7. Parallel Programming Parameters, Pin Mapping, and Commands 33.7.1. Signal Names 33.8. Parallel Programming 33.8.1. Enter Programming Mode 33.8.2. Considerations for Efficient Programming 33.8.3. Chip Erase 33.8.4. Programming the Flash 33.8.5. Programming the EEPROM 33.8.6. Reading the Flash 33.8.7. Reading the EEPROM 33.8.8. Programming the Fuse Low Bits 33.8.9. Programming the Fuse High Bits 33.8.10. Programming the Extended Fuse Bits 33.8.11. Programming the Lock Bits 33.8.12. Reading the Fuse and Lock Bits 33.8.13. Reading the Signature Bytes 33.8.14. Reading the Calibration Byte 33.8.15. Parallel Programming Characteristics 33.9. Serial Downloading 33.9.1. Serial Programming Pin Mapping 33.9.2. Serial Programming Algorithm 33.9.3. Serial Programming Instruction Set 33.9.4. SPI Serial Programming Characteristics 34. Electrical Characteristics 34.1. Absolute Maximum Ratings 34.2. DC Characteristics 34.2.1. Power Consumption 34.3. Speed Grades 34.4. Clock Characteristics 34.4.1. Calibrated Internal RC Oscillator Accuracy 34.4.2. External Clock Drive Waveforms 34.4.3. External Clock Drive 34.5. System and Reset Characteristics 34.6. SPI Timing Characteristics 34.7. Two-wire Serial Interface Characteristics 34.8. ADC Characteristics 34.9. Parallel Programming Characteristics 35. Typical Characteristics 35.1. Active Supply Current 35.2. Idle Supply Current 35.3. ATmega328PB Supply Current of IO Modules 35.4. Power-down Supply Current 35.5. Pin Pull-Up 35.6. Pin Driver Strength 35.7. Pin Threshold and Hysteresis 35.8. BOD Threshold 35.9. Analog Comparator Offset 35.10. Internal Oscillator Speed 35.11. Current Consumption of Peripheral Units 35.12. Current Consumption in Reset and Reset Pulse Width 36. Register Summary 37. Instruction Set Summary 38. Packaging Information 38.1. 32A 38.2. 32MS1 39. Errata 39.1. Rev. A 39.2. Rev. B 39.3. Rev. C 40. Revision History