Datasheet 74HC590
| Beschreibung | 8-bit binary counter with output register; 3-state |
| Seiten / Seite | 21 / 1 — 74HC590 8-bit binary counter with output register; 3-state. Rev. 02 — 28 … |
| Dateiformat / Größe | PDF / 502 Kb |
| Dokumentensprache | Englisch |
74HC590 8-bit binary counter with output register; 3-state. Rev. 02 — 28 April 2009. Product data sheet. General description
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74HC590 8-bit binary counter with output register; 3-state Rev. 02 — 28 April 2009 Product data sheet 1. General description
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register.
2. Features
n Counter and register have independent clock inputs n Counter has master reset n Complies with JEDEC standard no. 7A n Multiple package options n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 2000 V n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version
74HC590N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC590D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC590PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body SOT403-1 width 4.4 mm 74HC590BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1 quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm Document Outline 1. General description 2. Features 3. Ordering information 4. Functional diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 6. Functional description 7. Limiting values 8. Recommended operating conditions 9. Static characteristics 10. Dynamic characteristics 11. Waveforms 12. Package outline 13. Abbreviations 14. Revision history 15. Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks 16. Contact information 17. Contents
The 74HC590 is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features a master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state always is one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. If both clocks are connected together, the counter state always is one count ahead of the register.
2. Features
n Counter and register have independent clock inputs n Counter has master reset n Complies with JEDEC standard no. 7A n Multiple package options n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 2000 V n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version
74HC590N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC590D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC590PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body SOT403-1 width 4.4 mm 74HC590BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin SOT763-1 quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm Document Outline 1. General description 2. Features 3. Ordering information 4. Functional diagram 5. Pinning information 5.1 Pinning 5.2 Pin description 6. Functional description 7. Limiting values 8. Recommended operating conditions 9. Static characteristics 10. Dynamic characteristics 11. Waveforms 12. Package outline 13. Abbreviations 14. Revision history 15. Legal information 15.1 Data sheet status 15.2 Definitions 15.3 Disclaimers 15.4 Trademarks 16. Contact information 17. Contents