Datasheet AD9680 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter |
| Seiten / Seite | 91 / 2 — AD9680. Data Sheet. TABLE OF CONTENTS |
| Revision | E |
| Dateiformat / Größe | PDF / 4.0 Mb |
| Dokumentensprache | Englisch |
AD9680. Data Sheet. TABLE OF CONTENTS
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 1 link to page 1 link to page 1 link to page 1 link to page 3 link to page 4 link to page 5 link to page 5 link to page 6 link to page 8 link to page 9 link to page 9 link to page 11 link to page 11 link to page 11 link to page 12 link to page 14 link to page 14 link to page 19 link to page 24 link to page 28 link to page 30 link to page 30 link to page 30 link to page 35 link to page 36 link to page 38 link to page 38 link to page 38 link to page 39 link to page 40 link to page 42 link to page 42 link to page 42 link to page 42 link to page 48 link to page 48 link to page 49 link to page 49 link to page 51 link to page 51 link to page 52 link to page 54 link to page 54 link to page 55 link to page 58 link to page 58 link to page 58 link to page 59 link to page 59 link to page 61 link to page 63 link to page 65 link to page 68 link to page 70 link to page 72 link to page 72 link to page 73 link to page 75 link to page 75 link to page 75 link to page 75 link to page 76 link to page 76 link to page 77 link to page 90 link to page 90 link to page 90 link to page 90 link to page 91 link to page 91
AD9680 Data Sheet TABLE OF CONTENTS
Features .. 1 General Description ... 48 Applications ... 1 DDC NCO Plus Mixer Loss and SFDR ... 49 Functional Block Diagram .. 1 Numerically Controlled Oscillator .. 49 Product Highlights ... 1 FIR Filters .. 51 Revision History ... 3 General Description ... 51 General Description ... 4 Half-Band Filters .. 52 Specifications ... 5 DDC Gain Stage ... 54 DC Specifications ... 5 DDC Complex to Real Conversion ... 54 AC Specifications .. 6 DDC Example Configurations ... 55 Digital Specifications ... 8 Digital Outputs ... 58 Switching Specifications .. 9 Introduction to the JESD204B Interface ... 58 Timing Specifications .. 9 JESD204B Overview .. 58 Absolute Maximum Ratings .. 11 Functional Overview ... 59 Thermal Characteristics .. 11 JESD204B Link Establishment ... 59 ESD Caution .. 11 Physical Layer (Driver) Outputs .. 61 Pin Configuration and Function Descriptions ... 12 JESD204B Tx Converter Mapping ... 63 Typical Performance Characteristics ... 14 Configuring the JESD204B Link .. 65 AD9680-1000 .. 14 Multichip Synchronization .. 68 AD9680-820 .. 19 SYSREF± Setup/Hold Window Monitor ... 70 AD9680-500 .. 24 Test Modes ... 72 Equivalent Circuits ... 28 ADC Test Modes .. 72 Theory of Operation .. 30 JESD204B Block Test Modes .. 73 ADC Architecture .. 30 Serial Port Interface .. 75 Analog Input Considerations .. 30 Configuration Using the SPI ... 75 Voltage Reference ... 35 Hardware Interface ... 75 Clock Input Considerations .. 36 SPI Accessible Features .. 75 ADC Overrange and Fast Detect .. 38 Memory Map .. 76 ADC Overrange .. 38 Reading the Memory Map Register Table ... 76 Fast Threshold Detection (FD_A and FD_B) .. 38 Memory Map Register Table ... 77 Signal Monitor .. 39 Applications Information .. 90 SPORT Over JESD204B ... 40 Power Supply Recommendations ... 90 Digital Downconverter (DDC) ... 42 Exposed Pad Thermal Heat Slug Recommendations .. 90 DDC I/Q Input Selection .. 42 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .. 90 DDC I/Q Output Selection ... 42 Outline Dimensions ... 91 DDC General Description .. 42 Ordering Guide .. 91 Frequency Translation ... 48 Rev. B | Page 2 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE
AD9680 Data Sheet TABLE OF CONTENTS
Features .. 1 General Description ... 48 Applications ... 1 DDC NCO Plus Mixer Loss and SFDR ... 49 Functional Block Diagram .. 1 Numerically Controlled Oscillator .. 49 Product Highlights ... 1 FIR Filters .. 51 Revision History ... 3 General Description ... 51 General Description ... 4 Half-Band Filters .. 52 Specifications ... 5 DDC Gain Stage ... 54 DC Specifications ... 5 DDC Complex to Real Conversion ... 54 AC Specifications .. 6 DDC Example Configurations ... 55 Digital Specifications ... 8 Digital Outputs ... 58 Switching Specifications .. 9 Introduction to the JESD204B Interface ... 58 Timing Specifications .. 9 JESD204B Overview .. 58 Absolute Maximum Ratings .. 11 Functional Overview ... 59 Thermal Characteristics .. 11 JESD204B Link Establishment ... 59 ESD Caution .. 11 Physical Layer (Driver) Outputs .. 61 Pin Configuration and Function Descriptions ... 12 JESD204B Tx Converter Mapping ... 63 Typical Performance Characteristics ... 14 Configuring the JESD204B Link .. 65 AD9680-1000 .. 14 Multichip Synchronization .. 68 AD9680-820 .. 19 SYSREF± Setup/Hold Window Monitor ... 70 AD9680-500 .. 24 Test Modes ... 72 Equivalent Circuits ... 28 ADC Test Modes .. 72 Theory of Operation .. 30 JESD204B Block Test Modes .. 73 ADC Architecture .. 30 Serial Port Interface .. 75 Analog Input Considerations .. 30 Configuration Using the SPI ... 75 Voltage Reference ... 35 Hardware Interface ... 75 Clock Input Considerations .. 36 SPI Accessible Features .. 75 ADC Overrange and Fast Detect .. 38 Memory Map .. 76 ADC Overrange .. 38 Reading the Memory Map Register Table ... 76 Fast Threshold Detection (FD_A and FD_B) .. 38 Memory Map Register Table ... 77 Signal Monitor .. 39 Applications Information .. 90 SPORT Over JESD204B ... 40 Power Supply Recommendations ... 90 Digital Downconverter (DDC) ... 42 Exposed Pad Thermal Heat Slug Recommendations .. 90 DDC I/Q Input Selection .. 42 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .. 90 DDC I/Q Output Selection ... 42 Outline Dimensions ... 91 DDC General Description .. 42 Ordering Guide .. 91 Frequency Translation ... 48 Rev. B | Page 2 of 91 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1000 AD9680-820 AD9680-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT OVER JESD204B DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B TX CONVERTER MAPPING CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Four DDCs) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE