Datasheet ADA4961 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | Low Distortion, 3.2 GHz, RF DGA |
| Seiten / Seite | 24 / 5 — Data Sheet. ADA4961. 3.3 V Supply, Low. 5.0 V Supply, High. Power Mode. … |
| Revision | B |
| Dateiformat / Größe | PDF / 904 Kb |
| Dokumentensprache | Englisch |
Data Sheet. ADA4961. 3.3 V Supply, Low. 5.0 V Supply, High. Power Mode. Performance. Operation1. Mode Operation. Parameter
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Data Sheet ADA4961 3.3 V Supply, Low 5.0 V Supply, High Power Mode Performance Operation1 Mode Operation Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit
Third-Order Intermodulation VOUT = 1.2 V p-p composite (2 MHz Distortion (IMD3) spacing) Maximum gain −79 −85 dBc Minimum gain −77 −84 dBc 1 dB Compression Point (OP1dB) AV = 15 dB 16.4 18.8 dBm Noise Figure (NF) AV = 15 dB 6.0 6.3 dB Noise Density Referred to Output AV = 15 dB −153 −153 dBm/Hz (RTO) AC PERFORMANCE, 2 GHz Second Harmonic (HD2) Maximum gain −73 −75 dBc Minimum gain −76 −77 dBc Third Harmonic (HD3) Maximum gain −65 −70 dBc Minimum gain −66 −69 dBc Third-Order Intermodulation VOUT = 1.2 V p-p composite (2 MHz Distortion (IMD3) spacing) Maximum gain −64 −70 dBc Minimum gain −65 −70 dBc 1 dB Compression Point (OP1dB) AV = 15 dB 14.5 17.0 dBm Noise Figure (NF) AV = 15 dB 8.8 9.0 dB Noise Density Referred to Output AV = 15 dB −150 −150 dBm/Hz (RTO) 1 3.3 V high performance mode is not recommended because IMD performance degrades at hot temperatures.
TIMING SPECIFICATIONS Table 3. Parameter Description Min Typ Max Unit
tCLK Serial Clock Period 50 ns tDS Setup Time Between Data and Rising Edge of SCLK 5 ns tDH Hold Time Between Data and Rising Edge of SCLK 5 ns tS Setup Time Between Falling Edge of CS and SCLK ns tH Hold Time Between Rising Edge of CS and SCLK ns tHIGH Minimum Period SCLK Can Be in Logic High State 25 ns tLOW Minimum Period SCLK Can Be in Logic Low State 25 ns tACCESS Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for a Read Operation ns tZ Maximum Time Delay Between CS Deactivation and SDIO Bus Return to High Impedance ns
Timing Diagram CS tLOW tS t t t HIGH CLK H SCLK tACCESS tDH tDS tZ
002
SDIO
12454- Figure 2. Rev. A | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE/HARMONIC PERFORMANCE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS AC CHARACTERIZATION OUTPUT FILTER THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
Third-Order Intermodulation VOUT = 1.2 V p-p composite (2 MHz Distortion (IMD3) spacing) Maximum gain −79 −85 dBc Minimum gain −77 −84 dBc 1 dB Compression Point (OP1dB) AV = 15 dB 16.4 18.8 dBm Noise Figure (NF) AV = 15 dB 6.0 6.3 dB Noise Density Referred to Output AV = 15 dB −153 −153 dBm/Hz (RTO) AC PERFORMANCE, 2 GHz Second Harmonic (HD2) Maximum gain −73 −75 dBc Minimum gain −76 −77 dBc Third Harmonic (HD3) Maximum gain −65 −70 dBc Minimum gain −66 −69 dBc Third-Order Intermodulation VOUT = 1.2 V p-p composite (2 MHz Distortion (IMD3) spacing) Maximum gain −64 −70 dBc Minimum gain −65 −70 dBc 1 dB Compression Point (OP1dB) AV = 15 dB 14.5 17.0 dBm Noise Figure (NF) AV = 15 dB 8.8 9.0 dB Noise Density Referred to Output AV = 15 dB −150 −150 dBm/Hz (RTO) 1 3.3 V high performance mode is not recommended because IMD performance degrades at hot temperatures.
TIMING SPECIFICATIONS Table 3. Parameter Description Min Typ Max Unit
tCLK Serial Clock Period 50 ns tDS Setup Time Between Data and Rising Edge of SCLK 5 ns tDH Hold Time Between Data and Rising Edge of SCLK 5 ns tS Setup Time Between Falling Edge of CS and SCLK ns tH Hold Time Between Rising Edge of CS and SCLK ns tHIGH Minimum Period SCLK Can Be in Logic High State 25 ns tLOW Minimum Period SCLK Can Be in Logic Low State 25 ns tACCESS Maximum Time Delay Between Falling Edge of SCLK and Output Data Valid for a Read Operation ns tZ Maximum Time Delay Between CS Deactivation and SDIO Bus Return to High Impedance ns
Timing Diagram CS tLOW tS t t t HIGH CLK H SCLK tACCESS tDH tDS tZ
002
SDIO
12454- Figure 2. Rev. A | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS NOISE/HARMONIC PERFORMANCE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS AC CHARACTERIZATION OUTPUT FILTER THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LOW-PASS ANTIALIAS FILTERING FOR THE ADC INTERFACE LAYOUT CONSIDERATIONS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE