Datasheet ACT 1 (Actel) - 5

A C T ™ 1 S e r i e s F P G A s P i n D e s c r i p t i o n PRA Probe A (Output)
The Probe A pin is used to output data from any user-defined
CLK Clock (Input)
design node within the device. This independent diagnostic TTL Clock input for global clock distribution network. The pin is used in conjunction with the Probe B pin to allow Clock input is buffered prior to clocking the logic modules. real-time diagnostic output of any signal path within the This pin can also be used as an I/O. device. The Probe A pin can be used as a user-defined I/O
DCLK Diagnostic Clock (Input)
when debugging has been completed. The pin’s probe TTL Clock input for diagnostic probe and device capabilities can be permanently disabled to protect the programming. DCLK is active when the MODE pin is HIGH. programmed design’s confidentiality. PRA is active when the This pin functions as an I/O when the MODE pin is LOW. MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW.
GND Ground
Input LOW supply voltage.
PRB Probe B (Output)
The Probe B pin is used to output data from any user-defined
I/O Input/Output (Input, Output)
design node within the device. This independent diagnostic I/O pin functions as an input, output, three-state, or pin is used in conjunction with the Probe A pin to allow bidirectional buffer. Input and output levels are compatible real-time diagnostic output of any signal path within the with standard TTL and CMOS specifications. Unused I/O pins device. The Probe B pin can be used as a user-defined I/O are automatically driven LOW by the ALS software. when debugging has been completed. The pin’s probe
MODE Mode (Input)
capabilities can be permanently disabled to protect the The MODE pin controls the use of multifunction pins (DCLK, programmed design’s confidentiality. PRB is active when the PRA, PRB, SDI). When the MODE pin is HIGH, the special MODE pin is HIGH. This pin functions as an I/O when the functions are active. When the MODE pin is LOW, the pins MODE pin is LOW. function as I/O. To provide Actionprobe capability, the MODE
SDI Serial Data Input (Input)
pin should be terminated to GND through a 10K resistor so Serial data input for diagnostic probe and device that the MODE pin can be pulled high when required. programming. SDI is active when the MODE pin is HIGH. This
NC No Connection
pin functions as an I/O when the MODE pin is LOW. This pin is not connected to circuitry within the device.
VCC Supply Voltage
Input HIGH supply voltage.
A b s o l u t e M a x i m u m R a t i n g s
1
R e c o m m e n d e d O p e r a t i n g C o n d i t i o n s Free air temperature range Parameter Commercial Industrial Military Units Symbol Parameter Limits Units
Temperature 0 to –40 to –55 to Range1 +70 +85 +125 °C V 2 CC DC Supply Voltage –0.5 to +7.0 Volts Power Supply VI Input Voltage –0.5 to VCC +0.5 Volts Tolerance ±5 ±10 ±10 %VCC VO Output Voltage –0.5 to VCC +0.5 Volts
Note:
I ± IO I/O Sink/Source 20 mA 1. Ambient temperature (TA) used for commercial and industrial; Current3 case temperature (TC) used for military. T ° STG Storage Temperature –65 to +150 C
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. VPP = VCC , except during device programming. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diode will be forward biased and can draw excessive current.
1-287
Document Outline ACT™ 1 Series FPGAs Features Description Product Family Profile The Designer and Designer Advantage™ Systems ACT 1 Device Structure The ACT 1 Logic Module I/O Buffers Device Organization Probe Pin ACT 1 Array Performance Temperature and Voltage Effects Logic Module Size Ordering Information Product Plan Device Resources Pin Description Absolute Maximum Ratings1 Free air temperature range Recommended Operating Conditions Electrical Specifications (5V) Electrical Specifications (3.3V) Package Thermal Characteristics General Power Equation Static Power Component Active Power Component Equivalent Capacitance CEQ Values for Actel FPGAs Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Functional Timing Tests Output Buffer Performance Derating (5V) Output Buffer Performance Derating (3.3V) ACT 1 Timing Module* Predictable Performance: Tight Delay Distributions... Timing Characteristics Critical Nets and Typical Nets Long Tracks Timing Derating Timing Derating Factor (Temperature and Voltage) Timing Derating Factor for Designs at Typical Temp... Temperature and Voltage Derating Factors (normaliz... Temperature and Voltage Derating Factors (normaliz... Junction Temperature and Voltage Derating Curves (... Parameter Measurement Output Buffer Delays AC Test Loads Input Buffer Delays Module Delays Sequential Timing Characteristics Flip-Flops and Latches ACT 1 Timing Characteristics (Worst-Case Commercial Conditions, VCC = 4.75 V,T... ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) ACT 1 Timing Characteristics (continued) (Worst-Case Commercial Conditions) Package Pin Assignments 44-Pin PLCC 68-Pin PLCC Package Pin Assignments (continued) 84-Pin PLCC Package Pin Assignments (continued) 100-Pin PQFP Package Pin Assignments (continued) 80-Pin VQFP Package Pin Assignments (continued) 84-Pin CPGA Package Pin Assignments (continued) 84-Pin CQFP