Datasheet MAX5436, MAX5437, MAX5438, MAX5439 (Analog Devices) - 3

±15V, 128-Tap, Low-Drift Digital Potentiometers MAX5436–MAX5439 ELECTRICAL CHARACTERISTICS (continued)
(VDD = +15V, VSS = -15V, VCC = +5V, VH = VDD, VL = VSS, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VCC = 2.7V to 3.6V 2.0 V Input Low Voltage VCC = 2.7V to 3.6V 0.6 V Input Leakage Current ±1.0 µA Input Capacitance 5.0 pF
DYNAMIC CHARACTERISTICS (analog)
RHL = 50kΩ, midscale, VH = 1.5VP-P, 400 CWIPER = 20pF, voltage-divider mode Wiper -3dB Bandwidth BWW kHz RHL = 100kΩ, midscale, VH = 1.5VP-P, 200 CWIPER = 20pF, voltage-divider mode C Wiper Settling Time t WIPER = 20pF, code 1 to code 127, settle IL 5 µs to 0.5LSB
AMPLIFIER CHARACTERISTICS (analog)
Input Bias Current IB 15 nA Input Offset Voltage VOS ±6 mV Offset-Voltage Temperature Drift VOSD 10 µV/°C Input Offset Current IOS 2 nA Unity-Gain Bandwidth UBWA CLOAD = 250pF 100 kHz Slew Rate SR 0.25 V/µs Large-Signal Voltage Gain AVO RLOAD = 100kΩ, VOUT = ±14V 100 V/mV Input Noise VN f = 1kHz 110 nV/√Hz Input Compliance CMRI VSS + 1 VDD - 2 V Output Compliance CMRO ILOAD = ±5mA VSS + 1 VDD - 1 V DC CMRR CMRR 68 dB DC PSRR PSRR 70 dB
TIMING CHARACTERISTICS (digital)
(Note 5, Figure 3) SCLK Clock Frequency fCLK 0 10 MHz SCLK Clock Period tCP 100 ns SCLK Pulse Width High tCH 40 ns SCLK Pulse Width Low tCL 40 ns CS Fall to SCLK Rise Setup Time tCSS 40 ns SCLK Rise to CS Rise Hold Time tCSH 10 ns DIN Setup Time tDS 40 ns DIN Hold Time tDH 0 ns SCLK Rise to CS Fall Delay tCSO 10 ns CS Rise to SCLK Rise Hold tCS1 40 ns CS Pulse Width High tCSW 100 ns
POWER SUPPLIES
Positive Analog Supply Voltage VDD 0 31.5 V Negative Analog Supply Voltage VSS -28.8 0 V
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