Datasheet OPA205, OPA2205, OPA4205 (Texas Instruments) - 9

OPA205 , OPA2205 , OPA4205 www.ti.com
SBOS962F – APRIL 2020 – REVISED MARCH 2023
6.7 Electrical Characteristics: VS = ±5 V (continued)
at TA = 25°C, VCM = VOUT = midsupply, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN-LOOP GAIN
OPA2205, RL = 10 kΩ 126 132 TA = –40°C to +125°C, (V–) + 200 mV < V R O < (V+) – 200 mV L = 2 kΩ 126 130 AOL Open-loop voltage gain dB OPAx205A, RL = 10 kΩ 126 132 TA = –40°C to +125°C, (V–) + 200 mV < V R O < (V+) – 200 mV L = 2 kΩ 126 130
FREQUENCY RESPONSE
GBW Gain-bandwidth product 3.6 MHz SR Slew rate 4-V step, gain = –1 3.2 V/μs Phase margin RL = 10 kΩ, CL = 25 pF 67 degrees To 0.024% (12-bit), Falling 2.2 tS Settling time 4-V step, gain = 1, μs C Rising 2.8 L = 30 pF Overload recovery time Gain = –10 0.3 μs Total harmonic distortion THD+N V + noise O = 5 VPP, gain = +1, f = 1 kHz, RL = 2 kΩ 0.0004 %
OUTPUT
RL = 10 kΩ (V–) + 0.2 (V+) – 0.2 Voltage output swing AOL > 126 dB RL = 2 kΩ (V–) + 0.2 (V+) – 0.2 V from rail TA = –40°C to +125°C, RL = 10 kΩ (V–) + 0.2 (V+) – 0.2 ISC Short-circuit current ±25 mA CLOAD Capacitive load drive See Typical Characteristics Open-loop output RO See Typical Characteristics impedance
POWER SUPPLY
Quiescent current per 220 240 IQ I μA amplifier O = 0 mA TA = –40°C to +125°C 310 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: OPA205 OPA2205 OPA4205 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information: OPA205 6.5 Thermal Information: OPA2205 6.6 Thermal Information: OPA4205 6.7 Electrical Characteristics: VS = ±5 V 6.8 Electrical Characteristics: VS = ±15 V 6.9 Typical Characteristics 7 Parameter Measurement Information 7.1 Typical Specifications and Distributions 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input Offset Trimming 8.3.2 Lower Input Bias With Super-Beta Inputs 8.3.3 Overload Power Limiter 8.3.4 EMI Rejection 8.4 Device Functional Modes 9 Application and Implementation 9.1 Application Information 9.2 Typical Applications 9.2.1 High-Precision Signal-Chain Input Buffer 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curves 9.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 9.2.3 Second-Order Low-Pass Filter 9.3 Power Supply Recommendations 9.4 Layout 9.4.1 Layout Guidelines 9.4.2 Layout Example 10 Device and Documentation Support 10.1 Device Support 10.1.1 Development Support 10.1.1.1 PSpice® for TI 10.2 Documentation Support 10.2.1 Related Documentation 10.3 Receiving Notification of Documentation Updates 10.4 Support Resources 10.5 Trademarks 10.6 Electrostatic Discharge Caution 10.7 Glossary 11 Mechanical, Packaging, and Orderable Information