Datasheet NE570 (ON Semiconductor) - 5
| Hersteller | ON Semiconductor |
| Beschreibung | Compandor |
| Seiten / Seite | 11 / 5 — NE570. BASIC CIRCUIT HOOK−UP AND OPERATION. Figure 5. Chip Block Diagram … |
| Dateiformat / Größe | PDF / 176 Kb |
| Dokumentensprache | Englisch |
NE570. BASIC CIRCUIT HOOK−UP AND OPERATION. Figure 5. Chip Block Diagram (1 of 2 Channels). Figure 7. Basic Compressor
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NE570 BASIC CIRCUIT HOOK−UP AND OPERATION
Figure 7 shows the hook−up for a compressor. This is Figure 5 shows the block diagram of one half of the chip, essentially an expander placed in the feedback loop of the op (there are two identical channels on the IC). The full−wave amp. The DG cell is set−up to provide AC feedback only, so averaging rectifier provides a gain control current, IG, for the a separate DC feedback loop is provided by the two RDC and variable gain (DG) cell. The output of the DG cell is a current CDC. The values of RDC will determine the DC bias at the which is fed to the summing node of the operational output of the op amp. The output will bias to: amplifier. Resistors are provided to establish circuit gain and R ) R DC1 DC2Ǔ set the output DC bias. V DC + ǒ 1 ) V OUT R REF 4 THD_TRIM R3 INV. IN R Ǔ V DC + ǒ1 ) DC TOT 1.8 V 8, 9 6, 11 5, 12 OUT 30 kW R R 2 3 20 kW 20 kW The output of the expander will bias up to: DG_CELL_IN − DG 7, 10 3, 14 R Ǔ R 3 4 + I V OUTPUT V DC + ǒ 1 ) V G REF R OUT REF 1 30 kW R 1.8 V 4 10 kW RECT_IN VCC: PIN 13 2, 15 GND: PIN 4 V DC + ǒ1 ) 20 kWǓ 1.8 V + 3.0 V OUT 1, 16 30 kW CRECT The output will bias to 3.0 V when the internal resistors are used. External resistors may be placed in series with R3,
Figure 5. Chip Block Diagram (1 of 2 Channels)
(which will affect the gain), or in parallel with R4 to raise the DC bias to any desired value. The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at R2 some voltage above ground. An internal band gap voltage DG reference provides a very stable, low noise 1.8 V reference denoted VREF. The non−inverting input of the op amp is tied R1 to VREF, and the summing nodes of the rectifier and DG cell (located at the right of R1 and R2) have the same potential. *C *C The THD_TRIM pin is also at the V RECT F REF potential. *R *R DC Figure 6 shows how the circuit is hooked up to realize an DC expander. The input signal, VIN, is applied to the inputs of *CDC both the rectifier and the DG cell. When the input signal *CIN R3 − drops by 6.0 dB, the gain control current will drop by a factor VIN VOUT of 2, and so the gain will drop 6 dB. The output level at V + V OUT R4 REF will thus drop 12 dB, giving us the desired 2−to−1 expansion. NOTES: ǒ R1R2IB Ǔ1 R GAIN = 3 2 R 2 3 VIN(avg.) I *C R B = 140 mA IN1 2 − DG * EXTERNAL COMPONENTS VOUT VREF + R
Figure 7. Basic Compressor
V 4 IN *C R IN2 1 *CRECT NOTES: 2 2 R3 VIN (Avg.) GAIN = R1 R2 IB IB = 140 mA * EXTERNAL COMPONENTS
Figure 6. Basic Expander http://onsemi.com 5
NE570 BASIC CIRCUIT HOOK−UP AND OPERATION
Figure 7 shows the hook−up for a compressor. This is Figure 5 shows the block diagram of one half of the chip, essentially an expander placed in the feedback loop of the op (there are two identical channels on the IC). The full−wave amp. The DG cell is set−up to provide AC feedback only, so averaging rectifier provides a gain control current, IG, for the a separate DC feedback loop is provided by the two RDC and variable gain (DG) cell. The output of the DG cell is a current CDC. The values of RDC will determine the DC bias at the which is fed to the summing node of the operational output of the op amp. The output will bias to: amplifier. Resistors are provided to establish circuit gain and R ) R DC1 DC2Ǔ set the output DC bias. V DC + ǒ 1 ) V OUT R REF 4 THD_TRIM R3 INV. IN R Ǔ V DC + ǒ1 ) DC TOT 1.8 V 8, 9 6, 11 5, 12 OUT 30 kW R R 2 3 20 kW 20 kW The output of the expander will bias up to: DG_CELL_IN − DG 7, 10 3, 14 R Ǔ R 3 4 + I V OUTPUT V DC + ǒ 1 ) V G REF R OUT REF 1 30 kW R 1.8 V 4 10 kW RECT_IN VCC: PIN 13 2, 15 GND: PIN 4 V DC + ǒ1 ) 20 kWǓ 1.8 V + 3.0 V OUT 1, 16 30 kW CRECT The output will bias to 3.0 V when the internal resistors are used. External resistors may be placed in series with R3,
Figure 5. Chip Block Diagram (1 of 2 Channels)
(which will affect the gain), or in parallel with R4 to raise the DC bias to any desired value. The circuit is intended for use in single power supply systems, so the internal summing nodes must be biased at R2 some voltage above ground. An internal band gap voltage DG reference provides a very stable, low noise 1.8 V reference denoted VREF. The non−inverting input of the op amp is tied R1 to VREF, and the summing nodes of the rectifier and DG cell (located at the right of R1 and R2) have the same potential. *C *C The THD_TRIM pin is also at the V RECT F REF potential. *R *R DC Figure 6 shows how the circuit is hooked up to realize an DC expander. The input signal, VIN, is applied to the inputs of *CDC both the rectifier and the DG cell. When the input signal *CIN R3 − drops by 6.0 dB, the gain control current will drop by a factor VIN VOUT of 2, and so the gain will drop 6 dB. The output level at V + V OUT R4 REF will thus drop 12 dB, giving us the desired 2−to−1 expansion. NOTES: ǒ R1R2IB Ǔ1 R GAIN = 3 2 R 2 3 VIN(avg.) I *C R B = 140 mA IN1 2 − DG * EXTERNAL COMPONENTS VOUT VREF + R
Figure 7. Basic Compressor
V 4 IN *C R IN2 1 *CRECT NOTES: 2 2 R3 VIN (Avg.) GAIN = R1 R2 IB IB = 140 mA * EXTERNAL COMPONENTS
Figure 6. Basic Expander http://onsemi.com 5