Datasheet ADG801, ADG802 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | <0.4 Ω CMOS 1.8 V to 5.5 V SPST Switches |
| Seiten / Seite | 16 / 9 — Data Sheet. ADG801/ADG802. TERMINOLOGY V. IINL (IINH). CS (Off). GND. CD … |
| Dateiformat / Größe | PDF / 299 Kb |
| Dokumentensprache | Englisch |
Data Sheet. ADG801/ADG802. TERMINOLOGY V. IINL (IINH). CS (Off). GND. CD (Off). CD, CS (On). CIN. VD (VS). tON. RON. tOFF. RFLAT(ON)
Modelllinie für dieses Datenblatt
Textversion des Dokuments
link to page 10
Data Sheet ADG801/ADG802 TERMINOLOGY V IINL (IINH) DD
The most positive power supply potential. Input current of the digital input.
I CS (Off) DD
Positive supply current. The off switch source capacitance is measured with reference to ground.
GND
Ground (0 V) reference.
CD (Off)
The off switch drain capacitance is measured with reference
S
to ground. The source terminal can be an input or an output.
CD, CS (On) D
The on switch capacitance is measured with reference The drain terminal can be an input or an output. to ground.
IN CIN
Logic control input. Digital input capacitance.
VD (VS) tON
Analog voltage on Terminal D and Terminal S. The delay between applying the digital control input and when
RON
the output switches on. See Figure 16. Ohmic resistance between Terminal D and Terminal S.
tOFF RFLAT(ON)
The delay between applying the digital control input and when The difference between the maximum and minimum value of the output switches off. on resistance as measured over the specified analog signal range.
Charge Injection IS (Off)
A measure of the glitch impulse transferred from the digital Source leakage current with the switch off. input to the analog output during switching.
ID (Off) Off Isolation
Drain leakage current with the switch off. A measure of unwanted signal coupling through an off switch.
ID, IS (On) Bandwidth
Channel leakage current with the switch on. The frequency at which the output is attenuated by 3 dB.
VINL On Response
Maximum input voltage for Logic 0. The frequency response of the on switch.
VINH Insertion Loss
Minimum input voltage for Logic 1. The loss due to the on resistance of the switch. Rev. B | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADG801/ADG802 TERMINOLOGY V IINL (IINH) DD
The most positive power supply potential. Input current of the digital input.
I CS (Off) DD
Positive supply current. The off switch source capacitance is measured with reference to ground.
GND
Ground (0 V) reference.
CD (Off)
The off switch drain capacitance is measured with reference
S
to ground. The source terminal can be an input or an output.
CD, CS (On) D
The on switch capacitance is measured with reference The drain terminal can be an input or an output. to ground.
IN CIN
Logic control input. Digital input capacitance.
VD (VS) tON
Analog voltage on Terminal D and Terminal S. The delay between applying the digital control input and when
RON
the output switches on. See Figure 16. Ohmic resistance between Terminal D and Terminal S.
tOFF RFLAT(ON)
The delay between applying the digital control input and when The difference between the maximum and minimum value of the output switches off. on resistance as measured over the specified analog signal range.
Charge Injection IS (Off)
A measure of the glitch impulse transferred from the digital Source leakage current with the switch off. input to the analog output during switching.
ID (Off) Off Isolation
Drain leakage current with the switch off. A measure of unwanted signal coupling through an off switch.
ID, IS (On) Bandwidth
Channel leakage current with the switch on. The frequency at which the output is attenuated by 3 dB.
VINL On Response
Maximum input voltage for Logic 0. The frequency response of the on switch.
VINH Insertion Loss
Minimum input voltage for Logic 1. The loss due to the on resistance of the switch. Rev. B | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE