Datasheet BUF802 (Texas Instruments) - 6

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BUF802
SBOS998C – JUNE 2021 – REVISED MARCH 2022
www.ti.com 6.5 Electrical Characteristics: Wide Bandwidth Mode (continued)
at TA = 25°C, VS = ±6V, RL = 100 Ω || 400 fF, RS = 25 Ω, VOCM = 0V (mid-supply), CLH and CLL tied to VS+ and VS– respectively, Wide Bandwidth Mode unless otherwise specified (R_Bias = 17.8 kΩ)
PARAMETER Test Condition MIN TYP MAX UNIT INPUT
ZIN Input impedance f = 100 MHz 50 || 2.4 GΩ || pF Input Clamp current rating Continous Current Rating 100 mA VCLH range(1) 0 VS+ V VCLL range(1) VS– 0 CLH Clamping Time Time taken to clamp VOUT to VCLH during overdrive 0.2 nsec CLL Clamping Time Time taken to clamp VOUT to VCLL during overdrive 0.2 f = 500 MHz 4.5 Input Voltage Range THD = – 40 dBc f = 1 GHz 2.1 VPP f = 2 GHz 1.2
OUTPUT
VS+ – 1.9 TA = 25℃ VS– + 3.4 Output Swing V VS+ – 2.0 TA = –40℃ to 85℃ VS– + 3.4 ZO Output impedance f = 100 MHz 1.2 Ω
AUXILIARY INPUT
0.18 0.26 V/V GAUX VOUT to In_Aux Gain TA = –40℃ to 85℃ 0.23 V/V Default voltage at In_Aux VS– + 2.3 VS– + 3 VS– + 3.8 V In_Aux Input Voltage Range VS– + 1.0 VS– + 5.0 V VOUT to In_Aux Bandwidth 800 MHz RHF Resistance between In_Bias to JFET source 100 kΩ
POWER SUPPLY
VS Operating voltage range ±4.5 ±6.5 V 34 37 IQ Quiescent current IOUT = 0 (R_bias = 17.8 kΩ) TA = –40℃ to 85℃ 35.5 mA CL Mode enabled 36 40 PSRR at 100 kHz on VS+ 49 PSRR Power-supply rejection ratio dB PSRR at 100 kHz on VS– 38 (1) The 0-V limits are for bipolar and balanced power supplies. For other supply configurations mid-supply will set the minimum limit for VCLH and maximum limit for VCLL 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: BUF802 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics: Wide Bandwidth Mode 6.6 Electrical Characteristics: Low Quiescent Current Mode 6.7 Typical Characteristics 7 Parameter Measurement Information 8 Detailed Description 8.1 Overview 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Input and Output Over-Voltage Clamp 8.3.2 Adjustable Quiescent Current 8.3.3 ESD Structure 8.4 Device Functional Modes 8.4.1 Buffer Mode (BF Mode) 8.4.2 Composite Loop Mode (CL Mode) 9 Application and Implementation 9.1 Application Information 9.2 Typical Application 9.2.1 Oscilloscope Front-End Amplifier Design 9.2.1.1 Design Requirements 9.2.1.2 Detailed Design Procedure 9.2.1.3 Application Curves 9.2.2 Transforming a Wide-Bandwidth, 50 Ω Input Signal Chain to High-Input Impedance 9.2.2.1 Detailed Design Results 9.2.2.2 Application Curves 10 Power Supply Recommendations 11 Layout 11.1 Layout Guidelines 11.2 Layout Example 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation 12.2 Receiving Notification of Documentation Updates 12.3 Support Resources 12.4 Trademarks 12.5 Electrostatic Discharge Caution 12.6 Glossary 13 Mechanical, Packaging, and Orderable Information