Datasheet ADRF5031 (Analog Devices) - 10

link to page 10 link to page 5 Data Sheet
ADRF5031 THEORY OF OPERATION
The ADRF5031 integrates a driver to perform logic functions inter- The power handling of the ADRF5031 derates with frequencies less nally and to provide the user with the advantage of a simplified than 1 MHz. See Figure 2 for derating of the RF power towards CMOS-/LVTTL-compatible control interface. There are two digital lower frequencies. control input pins (EN and CTRL) that determine which RF port is in the insertion loss state and in the isolation state. See Table 7 for the
POWER SUPPLY
control voltage truth table. The ADRF5031 requires that a positive supply voltage is applied to When the EN pin is logic high, all RF paths are in isolation state the VDD pin and a negative supply voltage to the VSS pin. Bypassing regardless of the logic state of other pin. The RFx ports are capacitors are recommended on the supply lines to minimize RF terminated to internal 50 Ω resistors, and RFC becomes reflective. coupling.
RF INPUT AND OUTPUT
The ideal power-up sequence is as follows: The RF ports (RFC, RF1, and RF2) are DC-coupled to 0 V, and no
1.
Connect GND. DC blocking is required at the RF ports when the RF line potential
2.
Power up VDD and VSS. Power up VSS after VDD to avoid is equal to 0 V. The RF ports are internally matched to 50 Ω. current transients on VDD during ramp up.
3.
Apply digital control inputs. The relative order of the control The ADRF5031 is bidirectional with equal power handling capabili- inputs is not important. However, powering the digital control ties. The RF input signal can be applied to the RFC port or the inputs before the V selected RFx throw port. DD supply can inadvertently forward bias and damage the internal ESD protection structures. To avoid this The insertion loss path conducts the RF signal between the select- damage, use a series 1 kΩ resistor to limit the current flowing ed RFx throw port and the RFC (common) port. The isolation paths into the control pin. Use pull-up or pull-down resistors if the provide high loss between the insertion loss path and the unselect- controller is in a high impedance state after VDD is powered up, ed RFx throw port. The unselected RFx port of the ADRF5031 is and the control pins are not driven to a valid logic state. nonreflective.
4.
Apply RF input signal.
Table 7. Control Voltage Truth Table Digital Control Input RFx Paths EN CTRL RF1 to RFC RF2 to RFC
Low Low Isolation (off) Insertion loss (on) Low High Insertion loss (on) Isolation (off) High Low or high Isolation (off) Isolation (off)
analog.com Rev. A | 10 of 12
Document Outline Features Applications Functional Block Diagram General Description Specifications Single-Supply Operation Absolute Maximum Ratings Thermal Resistance Power Derating Curve Electrostatic Discharge (ESD) Ratings ESD Ratings for the ADRF5031 ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Insertion Loss, Return Loss, and Isolation Input Power Compression and Third-Order Intercept Theory of Operation RF Input and Output Power Supply Applications Information Recommendations for PCB Design Outline Dimensions Ordering Guide Evaluation Boards