Datasheet MTP20N20E (ON Semiconductor) - 5

MTP20N20E POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when controlled. The lengths of various switching intervals (∆t) calculating td(on) and is read at a voltage corresponding to the are determined by how fast the FET input capacitance can on−state when calculating td(off). be charged by current from the generator. At high switching speeds, parasitic circuit elements The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths, charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is t = Q/I complex. The MOSFET output capacitance also G(AV) complicates the mathematics. And finally, MOSFETs have During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified. times may be approximated by the following: The resistive switching time variation versus gate tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If where the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize RG = the gate drive resistance common inductance in the drain and gate circuit loops and and Q2 and VGSP are read from the gate charge curve. is believed readily achievable with board mounted During the turn−on and turn−off delay times, gate current is components. Most power electronic loads are inductive; the not constant. The simplest calculation uses appropriate data in the figure is taken with a resistive load, which values from the capacitance curves in a standard equation for approximates an optimally snubbed inductive load. Power voltage change in an RC network. The equations are: MOSFETs may be safely operated into an inductive load; td(on) = RG Ciss In [VGG/(VGG − VGSP)] however, snubbing reduces switching losses. td(off) = RG Ciss In (VGG/VGSP) 5000 VDS = 0 V VGS = 0 V TJ = 25°C Ciss 4000 3000 ANCE (pF) Crss ACIT Ciss 2000 C, CAP 1000 Coss 010 5 0 5 10 15 20 25 VGS VDS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation http://onsemi.com 4