Datasheet STGAP3S6I (STMicroelectronics) - 6
| Hersteller | STMicroelectronics |
| Beschreibung | Galvanically Isolated 6/10 A Single Gate Drivers With Protection Features |
| Seiten / Seite | 32 / 6 — STGAP3S6I, STGAP3S6S, STGAP3SXI, STGAP3SXS. Electrical characteristics. … |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
STGAP3S6I, STGAP3S6S, STGAP3SXI, STGAP3SXS. Electrical characteristics. Table 5. Electrical characteristics. Symbol. Pin
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STGAP3S6I, STGAP3S6S, STGAP3SXI, STGAP3SXS Electrical characteristics 4 Electrical characteristics
Test conditions: TJ = 25 °C, VH = 15 V, VL = GNDISO, VDD = 5 V, unless otherwise specified.
Table 5. Electrical characteristics Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Dynamic characteristics
t Input to output propagation delay Don IN+, IN- (1) 55 75 95 ns ON t Input to output propagation delay Doff IN+, IN- (1) 55 75 95 ns OFF STGAP3S6x (1) - 20 - 20% to 80%, CL = 4.7 nF tr GOUT Rise time ns STGAP3SXx (1) - 20 - 20% to 80%, CL = 10 nF STGAP3S6x (1) - 18 - 80% to 20%, CL = 4.7 nF tf GOUT Fall time ns STGAP3SXx (1) - 18 - 80% to 20%, CL = 10 nF Pulse width distortion PWD GOUT tIN > 100 ns - 0 10 ns |tDon - tDoff| t IN+, IN-, INmin Minimum propagated input pulse - 20 - ns RST Common-mode transient CMTI (2) immunity VCM = 1200 V, see Figure 17 200 - - V/ns |dVISO/dt|
Supply voltage
VDDon VDD VDD UBLO turn-on threshold 2.85 2.95 3.05 V VDDoff VDD VDD UVLO turn-off threshold 2.60 2.80 2.95 V VDDhyst VDD VDD UVLO hysteresis 130 160 190 mV tVDD-RDY RDY VDD UVLO to RDY low delay See Figure 3 1.5 2.5 3.5 μs tVDD-GOUT GOUT VDD UVLO to GOUT low delay See Figure 3 1.6 2.6 3.6 μs IN+ = 0 1.2 2.0 2.5 IQDD VDD VDD quiescent supply current mA IN+ = RDY = VDD, IN- = GND 8 11 13 STGAP3SxSx 12.9 13.6 14.3 VHon VH VH UVLO turn-on threshold V STGAP3SxIx 11.4 11.9 12.5 STGAP3SxSx 12.2 12.8 13.4 VHoff VH VH UVLO turn-off threshold V STGAP3SxIx 10.6 11.1 11.5 VHhyst VH VH UVLO hysteresis 0.6 0.8 1.0 V tVH-RDY RDY VH UVLO to RDY low delay See Figure 4 10 15 20 μs tVH-GOUT GOUT VH UVLO to GOUT low delay See Figure 4 1.5 2.5 3.5 μs IQH VH VH quiescent supply current IN+ = GND 3 5 6 mA SafeClp GOUT GOUT active clamp IGOUT = 0.2 A, VH floating 1.9 2.0 2.3 V
DS14758
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Rev 1 page 6/32
Document Outline STGAP3S6I, STGAP3S6S, STGAP3SXI, STGAP3SXS @NA Cover image @NA Device summary Features Applications Description 1 Block diagram 2 Pin description and connection diagram 3 Device ratings 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Power supplies and UVLO 6.2 Power-up, power-down, and “safe state” 6.3 Control inputs 6.3.1 Anti cross conduction interlocking 6.4 Miller clamp function 6.4.1 Miller clamp driver 6.5 Desaturation protection 6.5.1 Adjustable soft turn-off function 6.6 Watchdog 6.7 Thermal shutdown protection 7 Typical application diagram 8 PCB layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Unused functions 10 Testing and characterization information 11 Package information 11.1 SO-16W package information 11.2 SO-16W suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures
STGAP3S6I, STGAP3S6S, STGAP3SXI, STGAP3SXS Electrical characteristics 4 Electrical characteristics
Test conditions: TJ = 25 °C, VH = 15 V, VL = GNDISO, VDD = 5 V, unless otherwise specified.
Table 5. Electrical characteristics Symbol Pin Parameter Test conditions Min. Typ. Max. Unit Dynamic characteristics
t Input to output propagation delay Don IN+, IN- (1) 55 75 95 ns ON t Input to output propagation delay Doff IN+, IN- (1) 55 75 95 ns OFF STGAP3S6x (1) - 20 - 20% to 80%, CL = 4.7 nF tr GOUT Rise time ns STGAP3SXx (1) - 20 - 20% to 80%, CL = 10 nF STGAP3S6x (1) - 18 - 80% to 20%, CL = 4.7 nF tf GOUT Fall time ns STGAP3SXx (1) - 18 - 80% to 20%, CL = 10 nF Pulse width distortion PWD GOUT tIN > 100 ns - 0 10 ns |tDon - tDoff| t IN+, IN-, INmin Minimum propagated input pulse - 20 - ns RST Common-mode transient CMTI (2) immunity VCM = 1200 V, see Figure 17 200 - - V/ns |dVISO/dt|
Supply voltage
VDDon VDD VDD UBLO turn-on threshold 2.85 2.95 3.05 V VDDoff VDD VDD UVLO turn-off threshold 2.60 2.80 2.95 V VDDhyst VDD VDD UVLO hysteresis 130 160 190 mV tVDD-RDY RDY VDD UVLO to RDY low delay See Figure 3 1.5 2.5 3.5 μs tVDD-GOUT GOUT VDD UVLO to GOUT low delay See Figure 3 1.6 2.6 3.6 μs IN+ = 0 1.2 2.0 2.5 IQDD VDD VDD quiescent supply current mA IN+ = RDY = VDD, IN- = GND 8 11 13 STGAP3SxSx 12.9 13.6 14.3 VHon VH VH UVLO turn-on threshold V STGAP3SxIx 11.4 11.9 12.5 STGAP3SxSx 12.2 12.8 13.4 VHoff VH VH UVLO turn-off threshold V STGAP3SxIx 10.6 11.1 11.5 VHhyst VH VH UVLO hysteresis 0.6 0.8 1.0 V tVH-RDY RDY VH UVLO to RDY low delay See Figure 4 10 15 20 μs tVH-GOUT GOUT VH UVLO to GOUT low delay See Figure 4 1.5 2.5 3.5 μs IQH VH VH quiescent supply current IN+ = GND 3 5 6 mA SafeClp GOUT GOUT active clamp IGOUT = 0.2 A, VH floating 1.9 2.0 2.3 V
DS14758
-
Rev 1 page 6/32
Document Outline STGAP3S6I, STGAP3S6S, STGAP3SXI, STGAP3SXS @NA Cover image @NA Device summary Features Applications Description 1 Block diagram 2 Pin description and connection diagram 3 Device ratings 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Power supplies and UVLO 6.2 Power-up, power-down, and “safe state” 6.3 Control inputs 6.3.1 Anti cross conduction interlocking 6.4 Miller clamp function 6.4.1 Miller clamp driver 6.5 Desaturation protection 6.5.1 Adjustable soft turn-off function 6.6 Watchdog 6.7 Thermal shutdown protection 7 Typical application diagram 8 PCB layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Unused functions 10 Testing and characterization information 11 Package information 11.1 SO-16W package information 11.2 SO-16W suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures