Datasheet AT89S53 (Microchip) - 7

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AT89S53 Table 3.
WCON—Watchdog Control Register WCON Address = 96H Reset Value = 0000 0010B PS2 PS1 PS0 reserved reserved DPS WDTRST WDTEN Bit 7 6 5 4 3 2 1 0
Symbol Function
PS2 Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16 PS1 ms. When all three bits are set to “1”, the nominal period is 2048 ms. PS0 DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the second bank, DP1 WDTRST Watchdog Timer Reset. Each time this bit is set to “1” by user software, a pulse is generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. The WDTRST bit is Write-Only. WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.
SPI Registers
Control and status bits for the Serial Periph-
Dual Data Pointer Registers
To facilitate accessing exter- eral Interface are contained in registers SPCR (shown in nal data memory, two banks of 16-bit Data Pointer Table 4) and SPSR (shown in Table 5). The SPI data bits Registers are provided: DP0 at SFR address locations are contained in the SPDR register. Writing the SPI data 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WCON register during serial data transfer sets the Write Collision selects DP0 and DPS = 1 selects DP1. The user should bit, WCOL, in the SPSR register. The SPDR is double buff- always initalize the DPS bit to the appropriate value before ered for writing and the values in SPDR are not changed by accessing the respective Data Pointer register. Reset.
Power Off Flag
The Power Off Flag (POF) is located at
Interrupt Registers
The global interrupt enable bit and the bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during individual interrupt enable bits are in the IE register. In power up. It can be set and reset under software control addition, the individual interrupt enable bit for the SPI is in and is not affected by RESET. the SPCR register. Two priorities can be set for each of the six interrupt sources in the IP register.
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0787E–MICRO–3/06 Document Outline Block Diagram Instruction Set Features Description Pin Description VCC GND Port 0 Port 1 Pin Description Port 2 Port 3 RST ALE/PROG PSEN EA/VPP XTAL1 XTAL2 Special Function Registers Data Memory - RAM Programmable Watchdog Timer Timer 0 and 1 Timer 2 Capture Mode Auto-reload (Up or Down Counter) Baud Rate Generator Programmable Clock Out UART Serial Peripheral Interface Interrupts Oscillator Characteristics Idle Mode Status of External Pins During Idle and Power-down Modes Power-down Mode Program Memory Lock Bits Lock Bit Protection Modes(1)(2) Programming the Flash Programming Interface Serial Downloading Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The max... Serial Programming Algorithm Serial Programming Instruction Flash Parallel Programming Modes Flash Programming and Verification Characteristics - Parallel Mode Flash Programming and Verification Waveforms - Parallel Mode Serial Downloading Waveforms Absolute Maximum Ratings* DC Characteristics AC Characteristics External Program and Data Memory Characteristics External Program Memory Read Cycle External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms(1) Float Waveforms(1) Ordering Information Pin Configurations