Datasheet MAX3280E, MAX3281E, MAX3283E, MAX3284E (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | ±15kV ESD-Protected 52Mbps, 3V to 5.5V, SOT23 RS-485/RS-422 True Fail-Safe Receivers |
| Seiten / Seite | 11 / 7 — Table 1. MAX3281E/MAX3283E Enable. Table. PART. ENABLE = HIGH ENABLE = … |
| Dateiformat / Größe | PDF / 1.1 Mb |
| Dokumentensprache | Englisch |
Table 1. MAX3281E/MAX3283E Enable. Table. PART. ENABLE = HIGH ENABLE = LOW. Low-Voltage Logic Levels. (MAX3284E only)
Modelllinie für dieses Datenblatt
Textversion des Dokuments
MAX3280E/MAX3281E/ ±15kV ESD-Protected 52Mbps, 3V to 5.5V, MAX3283E/MAX3284E SOT23 RS-485/RS-422 True Fail-Safe Receivers users design equipment that meets Level 3 of IEC 1000-
Table 1. MAX3281E/MAX3283E Enable
4-2, without additional ESD-protection components.
Table
The main difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current
PART ENABLE = HIGH ENABLE = LOW
in IEC 1000-4-2. Because series resistance is lower in MAX3281E Active High Z the IEC 1000-4-2 ESD test model (Figure 4a), the ESD- MAX3283E High Z Active withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 4b shows the current waveform for the ±8kV IEC
Low-Voltage Logic Levels
1000-4-2 Level 4 ESD Contact Discharge test. The Air-
(MAX3284E only)
Gap test involves approaching the device with a charger An increasing number of applications now operate at probe. The Contact Discharge method connects the low-voltage logic levels. To enable compatibility with probe to the device before the probe is energized. these low-voltage logic level applications, such as digital
Machine Model
FPGAs, the MAX3284E VL pin is a user-defined supply voltage that designates the voltage threshold for a logic The Machine Model for ESD testing uses a 200pF stor- high. age capacitor and zero-discharge resistance. It mimics the stress caused by handling during manufacturing and At lower VL voltages, the data rate will also be lower. assembly. All pins (not just the RS-485 inputs) require this A logic-high level of 1.65V will receive data at 20Mbps. protection during manufacturing. Therefore, the Machine Table 2 gives data rates at various voltages at VL. Model is less relevant to the I/O ports than are the Human
Table 2. MAX3284E Data Rate Table
Body Model and IEC 1000-4-2.
VCC = 3V TO 5.5V True Fail-Safe VL MAXIMUM DATA RATE
The MAX3280E/MAX3281E/MAX3283E/MAX3284E guar- antee a logic-high receiver output when the receiver inputs 1.65V 20Mbps are shorted or open, or when they are connected to a 2.2V 33Mbps terminated transmission line with all drivers disabled. This ≥3.3V 52Mbps guaranteed logic high is achieved by setting the receiver threshold between -50mV and -200mV. If the differential
Applications Information
receiver input voltage (VA - VB) is greater than or equal to -50mV, RO is logic high. If (V
Propagation Delay Matching
A - VB) is less than or equal to -200mV, RO is logic low. The MAX3280E/MAX3281E/MAX3283E/MAX3284E (VCC In the case of a terminated bus with all transmitters dis- = VL) exhibit propagation delays that are closely matched abled, the receiver’s differential input voltage is pulled to from one device to another, even between devices from ground by the termination. This results in a logic high with different production lots. This feature allows multiple data a 50mV minimum noise margin. Unlike previous fail-safe lines to receive data and clock signals with minimal skew devices, the -50mV to -200mV threshold complies with with respect to each other. Figure 5 shows the typical the ±200mV EIA/TIA-485 standard. propagation delays. Small receiver skew times, the differ- ence between the low-to-high and high-to-low propagation
Receiver Enable
delay, help maintain a symmetrical ratio (50% duty cycle).
(MAX3281E and MAX3283E only)
The receiver skew time | tPLH - tPHL | is under 2ns for The MAX3281E and MAX3283E feature a receiver out- either a 3.3V supply or a 5V supply. put enable (EN, MAX3281E or EN, MAX3283E) input
Multidrop Clock Distribution
that controls the receiver. The MAX3281E receiver enable (EN) pin is active high, meaning the receiver Low package-to-package skew (8ns max) makes the outputs are active when EN is high. The MAX3283E MAX3280E/MAX3281E/MAX3283E/MAX3284E receiver enable (EN) pin is active low. Receiver outputs (VCC = VL) ideal for multidrop clock distribution. When are high impedance when the MAX3281E’s EN pin is low distributing a clock signal to multiple circuits over long and when the MAX3283E’s EN pin is high. transmission lines, receivers in separate locations, and possibly at two different temperatures, would ideally www.maximintegrated.com Maxim Integrated │
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Table 1. MAX3281E/MAX3283E Enable
4-2, without additional ESD-protection components.
Table
The main difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current
PART ENABLE = HIGH ENABLE = LOW
in IEC 1000-4-2. Because series resistance is lower in MAX3281E Active High Z the IEC 1000-4-2 ESD test model (Figure 4a), the ESD- MAX3283E High Z Active withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 4b shows the current waveform for the ±8kV IEC
Low-Voltage Logic Levels
1000-4-2 Level 4 ESD Contact Discharge test. The Air-
(MAX3284E only)
Gap test involves approaching the device with a charger An increasing number of applications now operate at probe. The Contact Discharge method connects the low-voltage logic levels. To enable compatibility with probe to the device before the probe is energized. these low-voltage logic level applications, such as digital
Machine Model
FPGAs, the MAX3284E VL pin is a user-defined supply voltage that designates the voltage threshold for a logic The Machine Model for ESD testing uses a 200pF stor- high. age capacitor and zero-discharge resistance. It mimics the stress caused by handling during manufacturing and At lower VL voltages, the data rate will also be lower. assembly. All pins (not just the RS-485 inputs) require this A logic-high level of 1.65V will receive data at 20Mbps. protection during manufacturing. Therefore, the Machine Table 2 gives data rates at various voltages at VL. Model is less relevant to the I/O ports than are the Human
Table 2. MAX3284E Data Rate Table
Body Model and IEC 1000-4-2.
VCC = 3V TO 5.5V True Fail-Safe VL MAXIMUM DATA RATE
The MAX3280E/MAX3281E/MAX3283E/MAX3284E guar- antee a logic-high receiver output when the receiver inputs 1.65V 20Mbps are shorted or open, or when they are connected to a 2.2V 33Mbps terminated transmission line with all drivers disabled. This ≥3.3V 52Mbps guaranteed logic high is achieved by setting the receiver threshold between -50mV and -200mV. If the differential
Applications Information
receiver input voltage (VA - VB) is greater than or equal to -50mV, RO is logic high. If (V
Propagation Delay Matching
A - VB) is less than or equal to -200mV, RO is logic low. The MAX3280E/MAX3281E/MAX3283E/MAX3284E (VCC In the case of a terminated bus with all transmitters dis- = VL) exhibit propagation delays that are closely matched abled, the receiver’s differential input voltage is pulled to from one device to another, even between devices from ground by the termination. This results in a logic high with different production lots. This feature allows multiple data a 50mV minimum noise margin. Unlike previous fail-safe lines to receive data and clock signals with minimal skew devices, the -50mV to -200mV threshold complies with with respect to each other. Figure 5 shows the typical the ±200mV EIA/TIA-485 standard. propagation delays. Small receiver skew times, the differ- ence between the low-to-high and high-to-low propagation
Receiver Enable
delay, help maintain a symmetrical ratio (50% duty cycle).
(MAX3281E and MAX3283E only)
The receiver skew time | tPLH - tPHL | is under 2ns for The MAX3281E and MAX3283E feature a receiver out- either a 3.3V supply or a 5V supply. put enable (EN, MAX3281E or EN, MAX3283E) input
Multidrop Clock Distribution
that controls the receiver. The MAX3281E receiver enable (EN) pin is active high, meaning the receiver Low package-to-package skew (8ns max) makes the outputs are active when EN is high. The MAX3283E MAX3280E/MAX3281E/MAX3283E/MAX3284E receiver enable (EN) pin is active low. Receiver outputs (VCC = VL) ideal for multidrop clock distribution. When are high impedance when the MAX3281E’s EN pin is low distributing a clock signal to multiple circuits over long and when the MAX3283E’s EN pin is high. transmission lines, receivers in separate locations, and possibly at two different temperatures, would ideally www.maximintegrated.com Maxim Integrated │
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