Datasheet ICL7660S, ICL7660A (Renesas) - 8

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Detailed Description Theoretical Power Efficiency
The ICL7660S and ICL7660A contain all the necessary
Considerations
circuitry to complete a negative voltage converter, with the In theory, a voltage converter can approach 100% efficiency if exception of two external capacitors, which may be certain conditions are met: inexpensive 10µF polarized electrolytic types. The mode of operation of the device may best be understood by considering 1. The drive circuitry consumes minimal power. Figure 14, which shows an idealized negative voltage 2. The output switches have extremely low ON resistance and converter. Capacitor C virtually no offset. 1 is charged to a voltage, V+, for the half cycle, when switches S1 and S3 are closed. (Note: Switches 3. The impedance of the pump and reservoir capacitors are S negligible at the pump frequency. 2 and S4 are open during this half cycle). During the second half cycle of operation, switches S2 and S4 are closed, with S1 The ICL7660S and ICL7660A approach these conditions for and S3 open, thereby shifting capacitor C1 to C2 such that the negative voltage conversion if large values of C1 and C2 are voltage on C2 is exactly V+, assuming ideal switches and no used.
ENERGY IS LOST ONLY IN THE TRANSFER OF
load on C2. The ICL7660S and ICL7660A approach this ideal
CHARGE BETWEEN CAPACITORS IF A CHANGE IN
situation more closely than existing non-mechanical circuits.
VOLTAGE OCCURS
. The energy lost is defined as shown in
8 S 2
Equation 1:
1 S2 VIN
1 E = --C 2  V 2 –  (EQ. 1) 2 1 V1 2
C1 3 3
where V1 and V2 are the voltages on C1 during the pump and transfer cycles. If the impedances of C1 and C2 are relatively
C
high at the pump frequency (see Figure 14) compared to the
2
value of R
S 5
L, there will be a substantial difference in the
3 S4
voltages, V1 and V2. Therefore it is not only desirable to make
4 VOUT = -VIN
C2 as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C1 in order to achieve maximum efficiency of operation.
7 Do’s and Don’ts FIGURE 14. IDEALIZED NEGATIVE VOLTAGE CONVERTER
1. Do not exceed maximum supply voltages. In the ICL7660S and ICL7660A, the four switches of Figure 14 2. Do not connect LV terminal to GND for supply voltage are MOS power switches; S1 is a P-Channel device; and S2, greater than 3.5V. S3 and S4 are N-Channel devices. The main difficulty with this 3. Do not short circuit the output to V+ supply for supply approach is that in integrating the switches, the substrates of voltages above 5.5V for extended periods; however, S3 and S4 must always remain reverse biased with respect to transient conditions including start-up are okay. their sources, but not so much as to degrade their “ON” 4. When using polarized capacitors, the + terminal of C resistances. In addition, at circuit start-up, and under output 1 must be connected to pin 2 of the ICL7660S and ICL7660A, and short circuit conditions (VOUT = V+), the output voltage must the + terminal of C2 must be connected to GND. be sensed and the substrate bias adjusted accordingly. Failure 5. If the voltage supply driving the ICL7660S and ICL7660A to accomplish this would result in high power losses and has a large source impedance (25 to 30), then a 2.2µF probable device latch-up. capacitor from pin 8 to ground may be required to limit the This problem is eliminated in the ICL7660S and ICL7660A by a rate of rise of input voltage to less than 2V/µs. logic network that senses the output voltage (V 6. If the input voltage is higher than 5V and it has a rise rate OUT) together with the level translators, and switches the substrates of S more than 2V/µs, an external Schottky diode from V 3 and OUT to S CAP- is needed to prevent latchup (triggered by forward 4 to the correct level to maintain necessary reverse bias. biasing Q4’s body diode) by keeping the output (pin 5) from The voltage regulator portion of the ICL7660S and ICL7660A is going more positive than CAP- (pin 4). an integral part of the anti-latchup circuitry; however, its 7. User should ensure that the output (pin 5) does not go more inherent voltage drop can degrade operation at low voltages. positive than GND (pin 3). Device latch-up will occur under Therefore, to improve low voltage operation, the “LV” pin these conditions. To provide additional protection, a 1N914 should be connected to GND, thus disabling the regulator. For or similar diode placed in parallel with C2 will prevent the supply voltages greater than 3.5V, the LV terminal must be left device from latching up under these conditions, when the open to ensure latchup-proof operation and to prevent device load on VOUT creates a path to pull up VOUT before the IC damage. is active (anode pin 5, cathode pin 3). FN3179 Rev 7.01 Page 8 of 14 Feb 10, 2020