Datasheet L99H92 (STMicroelectronics) - 9

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L99H92 Gate drivers Figure 4. NRDY status bit and CPLOW flag
GADG120920220925SA
2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2)
When the OUTE control bit is reset with the FSINB pin high, all the gate drivers are disabled and the turned on MOSFETs are passively shut off through the internal resistance connected between gate and source of each MOSFET (RGSHx and RGSLx). Regardless of the OUTE control bit value, when the FSINB pin is pulled low all the MOSFETs are actively shut off by the gate drivers forced in sink switch mode. Once the OUTE control bit is set and the FSINB pin is high, the external MOSFETs are driven by the input pins PWM/IN1 and DIR/IN2. Both input pins, PWM/IN1 and DIR/IN2, have an internal pull-down current (IPWM_in and IDIR_in) to put the outputs in a well-known condition in case any of the pins will no longer be driven by the microcontroller. Depending on the value of the INPMODE control bit, the device can work as full-bridge driver or dual half-bridge driver: • If INPMODE = 0 (default value), the device works in full-bridge mode. In this case the active full-bridge diagonal, fixing the rotational direction of the motor is selected by DIR/IN2 input while the driving PWM signal has to be applied to PWM/IN1 input. Depending on the active free-wheeling enable control bit value (AFWE) and the freewheeling selection control bit value (FWS), four different freewheeling strategies are available: active or passive and freewheeling on either high-side or low-side MOSFETs. The DIR input pin sets the active diagonal. The AFWE control bit enables or disables active free-wheeling and the FWS control bit sets the free-wheeling path (HS or LS).
Table 2. Truth table Device in active mode with INPMODE=0 (FULL-BRIDGE MODE) Inputs Outputs (in case of no faults) OUTE FWS FSINB DIR PWM AFWE bit HS1 LS1 HS2 LS2 bit bit pin pin pin
x x x 0(1) x x OFF OFF OFF OFF 0 x x 1 x x OFF(2) OFF(2) OFF(2) OFF(2) 1 0 0 1 0 0 OFF OFF OFF ON 1 x x 1 0 1 ON OFF OFF ON 1 0 1 1 0 0 ON OFF OFF OFF
DS14069
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Rev 4 page 9/77
Document Outline L99H92 Features Applications Description 1 Block diagram and pins description 1.1 Block diagram 1.2 Pinout 1.3 Pins description 2 Device description 2.1 Supply pins 2.1.1 VS overvoltage warning (VSOVW) 2.1.2 VDH overvoltage (VDHOV) 2.1.3 VDH undervoltage (VDHUV) 2.1.4 VDD overvoltage (VDDOV) 2.1.5 Digital input/output overvoltage (DIOOV) 2.1.6 Power-on reset (POR) 2.2 Standby mode (EN) 2.3 Active mode (OUTE) 2.4 Thermal warning and thermal shutdown (TW/TSD) 2.5 Charge pump (CPOUT) 2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2) 2.6.2 Slew rate control (SLEW) 2.6.3 Short circuit detection / drain-source monitoring (DSHS/DSLS) 2.6.4 Programmable cross current protection time (DT) 2.7 Diagnostic in off-mode (O1DS/O2DS) 2.8 Fail-safe output switch-off input not pin (FSINB) 2.9 Diagnostic not output (DIAGN) 2.10 Current monitors 2.11 Window watchdog (WDG) 3 Application 4 Serial peripheral interface (SPI) 4.1 ST SPI 4.1 4.1.1 Physical layer 4.1.2 Clock and data characteristics 4.1.3 Communication protocol 4.1.4 Address definition 5 Electrical characteristics 5.1 Absolute maximum ratings 5.2 ESD protection 5.3 Thermal data 5.4 Electrical characteristics 5.4.1 Supply, supply monitoring 5.4.2 Power-on reset 5.5 Charge pump 5.6 Full-bridge driver 5.7 VDS monitoring thresholds 5.7.1 Open-load monitoring external full-bridges 5.8 Current sense amplifiers (CSA) 5.9 Fail-safe switch-off input FSINB 5.10 Enable 5.11 DIAGN 5.12 Watchdog 5.13 SPI electrical characteristics 5.14 Oscillator 5.15 Operating modes 6 SPI registers 6.1 Global status byte GSB 6.2 Register map overview 6.3 Status registers 6.4 Control registers 7 Package information 7.1 QFN32L 5x5 mm package information 7.2 TQFP32L 7x7 mm package information Revision history