Datasheet L99H92 (STMicroelectronics) - 6

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L99H92 Device description 2 Device description 2.1 Supply pins
The device has three supply input pins: • VS is the supply input of the internal regulator that supplies the logic. • VDH is the supply input of the charge pump that supplies the gate drivers and the current sense amplifiers input stage. • VDD is the supply input of the I/Os and the current sense amplifiers output stage. This voltage has to be the same as the application microcontroller supply (for example, 3.3 V or 5 V). None of the supply input pins are internally protected against negative voltage. The VDD supply input can withstand a short to battery up to VDD absolute maximum rating as shown in Table 17.
2.1.1 VS overvoltage warning (VSOVW)
When the VS supply input voltage rises above the programmable overvoltage warning threshold (VSOVWT1 for OVTS=0 or VSOVWT2 for OVTS=1) for a time longer than tovuv_filt, then the corresponding overvoltage warning flag (VSOVW) is set, and no action is taken. The overvoltage warning flag VSOVW can be cleared by an SPI “Read & Clear” command only if the VS overvoltage condition is no longer present, namely if VS<VSOVWT1 or VS<VSOVWT2, depending on the OVTS control bit value, for a time longer than the corresponding filtering time tovuv_filt.
2.1.2 VDH overvoltage (VDHOV)
When the VDH supply input voltage rises above the programmable overvoltage protection threshold (VDHOVT1 for OVTS=0 or VDHOVT2 for OVTS=1) for a time longer than tovuv_filt, then the corresponding overvoltage flag (VDHOV) is set, and to protect the application the charge pump is disabled and the external MOSFETs are switched off. In particular, the LS MOSFETs gate drivers are forced in sink switch mode to switch off actively the LS MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits), whereas the HS MOSFETs gate drivers are forced in sink switch mode for 32 µs (up to 64 µs) and as long as VCP>VDH+3 V to switch off actively the HS MOSFETs with the maximum available current, regardless of the programmed gate discharge current. Once the 32 µs (up to 64 µs) are over or VCP<VDH+3 V the HS MOSFETs gate drivers are disabled leaving just an internal resistive connection (RGSHx) between gate and source of the MOSFETs. The charge pump is automatically enabled once the VDH falls back below the overvoltage protection threshold (VDHOVT1 for OVTS=0 or VDHOVT2 for OVTS=1) for a time longer than the corresponding filtering time tovuv_filt, while the LS MOSFETs gate drivers remain in sink switch mode and the HS MOSFETs gate drivers remain disabled until the VDHOV flag is cleared. The overvoltage protection flag VDHOV can be cleared by an SPI “Read & Clear” command only if the VDH overvoltage condition is no longer present, namely if the foresaid condition that automatically enables the charge pump is fulfilled.
2.1.3 VDH undervoltage (VDHUV)
When the VDH supply input voltage falls below the undervoltage protection threshold (VDHUV) for a time longer than tovuv_filt, then the corresponding undervoltage flag (VDHUV) is set, and to protect the external power stage the external MOSFETs are switched off. In particular, the LS MOSFETs gate drivers are forced in sink switch mode to switch off actively the LS MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx control bits). The HS MOSFETs gate drivers are forced in sink switch mode, as long as VCP>VDH+3 V, otherwise the HS MOSFETs gate drivers are disabled and the HS MOSFETs are passively switched off through the internal resistive connection between gate and source (RGSHx). The gate drivers come out of forced sink switch mode/disabled mode once the undervoltage flag VDHUV is cleared. The under-voltage flag VDHUV can be cleared by an SPI “Read & Clear” command only if the VDH undervoltage condition is no longer present, namely if VDH>VDHUV for a time longer than the corresponding filtering time tovuv_filt.
DS14069
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Rev 4 page 6/77
Document Outline L99H92 Features Applications Description 1 Block diagram and pins description 1.1 Block diagram 1.2 Pinout 1.3 Pins description 2 Device description 2.1 Supply pins 2.1.1 VS overvoltage warning (VSOVW) 2.1.2 VDH overvoltage (VDHOV) 2.1.3 VDH undervoltage (VDHUV) 2.1.4 VDD overvoltage (VDDOV) 2.1.5 Digital input/output overvoltage (DIOOV) 2.1.6 Power-on reset (POR) 2.2 Standby mode (EN) 2.3 Active mode (OUTE) 2.4 Thermal warning and thermal shutdown (TW/TSD) 2.5 Charge pump (CPOUT) 2.6 Gate drivers 2.6.1 Outputs driving signals (PWM/IN1 and DIR/IN2) 2.6.2 Slew rate control (SLEW) 2.6.3 Short circuit detection / drain-source monitoring (DSHS/DSLS) 2.6.4 Programmable cross current protection time (DT) 2.7 Diagnostic in off-mode (O1DS/O2DS) 2.8 Fail-safe output switch-off input not pin (FSINB) 2.9 Diagnostic not output (DIAGN) 2.10 Current monitors 2.11 Window watchdog (WDG) 3 Application 4 Serial peripheral interface (SPI) 4.1 ST SPI 4.1 4.1.1 Physical layer 4.1.2 Clock and data characteristics 4.1.3 Communication protocol 4.1.4 Address definition 5 Electrical characteristics 5.1 Absolute maximum ratings 5.2 ESD protection 5.3 Thermal data 5.4 Electrical characteristics 5.4.1 Supply, supply monitoring 5.4.2 Power-on reset 5.5 Charge pump 5.6 Full-bridge driver 5.7 VDS monitoring thresholds 5.7.1 Open-load monitoring external full-bridges 5.8 Current sense amplifiers (CSA) 5.9 Fail-safe switch-off input FSINB 5.10 Enable 5.11 DIAGN 5.12 Watchdog 5.13 SPI electrical characteristics 5.14 Oscillator 5.15 Operating modes 6 SPI registers 6.1 Global status byte GSB 6.2 Register map overview 6.3 Status registers 6.4 Control registers 7 Package information 7.1 QFN32L 5x5 mm package information 7.2 TQFP32L 7x7 mm package information Revision history