Datasheet STM32H7R3x8, STM32H7R7x8 (STMicroelectronics)

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STM32H7R3x8 STM32H7R7x8
Arm® Cortex®-M7 32-bit 600 MHz MCU, 64 KB flash, 620 KB RAM, Ethernet, 2x USB, 2x FD-CAN, advanced graphics, 2x12-bit ADCs
Datasheet
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production data Features Includes ST state-of-the-art patented technology
LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) LQFP176 (24 x 24 mm) UFBGA UFBGA
Core
UFBGA • 32-bit Arm® Cortex®-M7 CPU with MPU and DP-FPU, L1 cache: 32+32-Kbyte instruction UFBGA144 (10 x 10 mm) UFBGA169 (7 x 7 mm) UFBGA176+25 (10 x 10 mm) and data cache allowing 0-wait state execution TFBGA VFQFPN from embedded flash memory and external TFBGA memories, frequency up to 600 MHz, 1284 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1), and WLCSP101 (die) TFBGA100 (8x8 mm) TFBGA225 (13 x 13 mm) VFQFPN68 (10 x 10 mm) DSP instructions
Security Memories
• Flexible life cycle scheme with debug • 64 Kbytes of user flash memory that can be authentication based on certificate or password used for user code and/or external memory (debug reopening/regression support) configuration. • Root of trust thanks to unique boot entry and • SRAM: total 620 Kbytes (548 Kbytes with secure hide protection area (HDP) optional ECC activated) organized as follows: – 64+64 Kbytes minimum of instruction and • Secure firmware installation / update data TCM RAM for critical real time (SFI/SFU) thanks to embedded root secure instructions services (RSS) – 384 Kbytes AXI SRAM (128 Kbytes with • Public key accelerator, with ECC verification optional remap to TCM RAM fully activated feature only. – 4 Kbytes of backup SRAM (available in the • HASH hardware accelerator lowest-power modes) • True random number generator, NIST • Flexible external memory controller with up to SP800-90B compliant 32-bit data bus: SRAM, PSRAM, FRAM, • 96-bit unique ID SDR/LPSDR SDRAM, NOR/NAND memories • 1 Kbyte OTP (one-time programmable) • Up to 2x octo-SPI memory interfaces or 1 • Active tampers octo-SPI + 1 hexa-SPI with XiP, with support for serial PSRAM/NAND/NOR, HyperRAM™/ • Hardware secure storage (dedicated secure HyperFlash™ frame formats running at up to flash area) 200 MHz
Graphics
• 2x SD/SDIO/MMC interfaces • NeoChrom graphic processor (GPU2D) accelerating any angle rotation, scaling and
2x DMA controllers to offload the CPU
perspective correct texture mapping • 2 × dual-port DMAs with FIFO and linked listed • Chrom-ART Accelerator (DMA2D) for support enhanced graphic content creation March 2024 DS14360 Rev 2 1/315 This is information on a product in full production. www.st.com Document Outline Table 1. Device summary 1 Introduction 2 Description Table 2. Security and graphics IP availability per product line Figure 1. STM32H7Rxx8 block diagram Table 3. STM32H7Rxx8 features and peripheral counts (continued) 3 Functional overview 3.1 Arm Cortex-M7 with FPU 3.2 Memory protection unit (MPU) 3.3 Memories 3.3.1 Embedded flash memory 3.3.2 Secure access mode 3.3.3 Embedded SRAM 3.4 Boot modes 3.5 Power supply management 3.5.1 Power supply scheme Figure 2. System supply configurations 3.5.2 Power supply supervisor 3.5.3 Voltage regulator 3.5.4 SMPS step-down converter 3.6 Low-power modes Table 4. Operating mode summary Table 5. Overview of low-power mode monitoring pins 3.7 Reset and clock controller (RCC) Figure 3. Top-level clock tree Figure 4. Core and bus clock generation Table 6. Peripheral clock distribution summary (continued) 3.7.1 Clock management 3.7.2 System reset sources 3.8 General-purpose input/outputs (GPIOs) 3.9 Bus-interconnect matrix Figure 5. System architecture 3.10 General purpose / high-performance direct memory access controller (GPDMA/HPDMA) 3.11 Chrom-ART Accelerator (DMA2D) 3.12 NeoChrom graphic processor (GPU2D) 3.13 Chrom-GRC (GFXMMU) 3.14 Nested vectored interrupt controller (NVIC) 3.15 Extended interrupt and event controller (EXTI) 3.16 Cyclic redundancy check calculation unit (CRC) 3.17 CORDIC co-processor (CORDIC) 3.18 Flexible memory controller (FMC) 3.19 Quad/Octo/Hexa-SPI memory interface 3.19.1 XSPI I/O manager (XSPIM) Table 7. XSPIM implementation 3.19.2 Extended-SPI interface (XSPI) Table 8. XSPI implementation 3.20 Analog-to-digital converters (ADCs) 3.21 Analog temperature sensor Table 9. Temperature sensor calibration values 3.22 Digital temperature sensor (DTS) 3.23 VBAT operation 3.24 Voltage reference buffer (VREFBUF) 3.25 Audio digital filter (ADF) Table 10. ADF features 3.26 Digital camera interface (DCMIPP) 3.27 Parallel synchronous slave interface (PSSI) 3.28 LCD-TFT display controller 3.29 JPEG codec (JPEG) 3.30 Random number generator (RNG) 3.31 Hash processor (HASH) 3.32 Public key accelerator (PKA) 3.33 Timers and watchdogs Table 11. Timer feature comparison 3.33.1 Advanced-control timers (TIM1) 3.33.2 General-purpose timers (TIMx) 3.33.3 Basic timers TIM6 and TIM7 3.33.4 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5) 3.33.5 Independent watchdog 3.33.6 Window watchdog 3.33.7 SysTick timer 3.34 Real-time clock (RTC) 3.35 Tamper and backup registers (TAMP) 3.36 Inter-integrated circuit interface (I2C) 3.37 Improved inter-integrated circuit (I3C) 3.38 Universal synchronous/asynchronous receiver transmitter (USART/UART) and low-power universal asynchronous receiver transmitter (LPUART) Table 12. USART, UART and LPUART features 3.38.1 Universal synchronous/asynchronous receiver transmitter (USART/UART) Table 13. Instance implementation on STM32H7Rxx8 3.38.2 Low-power universal asynchronous receiver transmitter (LPUART) 3.39 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) 3.39.1 Introduction 3.39.2 SPI main features 3.39.3 SPI implementation Table 14. SPI features 3.40 Serial audio interfaces (SAI) 3.40.1 SAI main features 3.40.2 SAI implementation Table 15. STM32H7Rxx8 SAI features 3.41 SPDIFRX receiver interface (SPDIFRX) 3.42 Management data input/output (MDIO) slaves 3.43 Secure digital input/output MultiMediaCard interface (SDMMC) 3.44 Controller area network (FDCAN1, FDCAN2) 3.45 Universal serial bus on-the-go full-speed (OTG_FS) Table 16. OTG_FS speeds supported 3.46 Universal serial bus on-the-go high-speed (OTG_HS) Table 17. OTG_HS speeds supported 3.47 Ethernet MAC interface with dedicated DMA controller (ETH) 3.48 USB Type-C power delivery controller (UCPD) 3.49 High-definition multimedia interface - consumer electronics control (HDMI-CEC) 3.50 Development support 3.50.1 Serial-wire/JTAG debug port (SWJ-DP) 3.50.2 Embedded Trace Macrocell 4 Pinouts, pin description and alternate functions Figure 6. TFBGA100 SMPS pinout Figure 7. UFBGA144 SMPS pinout Figure 8. UFBGA169 SMPS pinout Figure 9. UFBGA144 GFx with SMPS pinout Figure 10. UFBGA169 GFx with SMPS pinout Figure 11. UFBGA176 SMPS pinout Figure 12. UFBGA176 SMPS GFx pinout Figure 13. LQFP176 SMPS pinout Figure 14. LQFP176 GFx with SMPS pinout Figure 15. WLCSP101 with SMPS pinout Figure 16. TFBGA225 OCTO with SMPS pinout Figure 17. TFBGA225 HEXA with SMPS pinout Figure 18. VFQFPN68 GP pinout Figure 19. LQFP100 GP pinout Figure 20. LQFP144 GP pinout 4.1 Pin description Table 18. Legend/abbreviations used in the pinout table Table 19. STM32H7Rxx8 pin and ball descriptions (continued) Table 20. STM32H7Rxx8 pin alternate functions (continued) 5 Memory mapping 6 Electrical characteristics 6.1 Parameter conditions 6.1.1 Minimum and maximum values 6.1.2 Typical values 6.1.3 Typical curves 6.1.4 Loading capacitor 6.1.5 Pin input voltage Figure 21. Pin loading conditions Figure 22. Pin input voltage 6.1.6 Power supply scheme Figure 23. Power supply scheme 6.1.7 Current consumption measurement Figure 24. Current consumption measurement scheme 6.2 Absolute maximum ratings Table 21. Voltage characteristics Table 22. Current characteristics Table 23. Thermal characteristics 6.3 Operating conditions 6.3.1 General operating conditions Table 24. General operating conditions (continued) Table 25. Supply voltage and maximum temperature configuration 6.3.2 VCAP external capacitor Figure 25. External capacitor CEXT Table 26. VCAP operating conditions 6.3.3 SMPS step-down converter Figure 26. External components for SMPS step-down converter Table 27. Characteristics of SMPS step-down converter external components Table 28. SMPS step-down converter characteristics for external usage Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS Figure 27. SMPS efficiency in VOS mode Tj=25°C Figure 28. SMPS efficiency in VOS mode Tj=125°C Figure 29. SMPS efficiency in SVOS mode Tj=25°C Figure 30. SMPS efficiency in SVOS mode Tj=125°C 6.3.4 Operating conditions at power-up / power-down Table 30. Operating conditions at power-up/power-down 6.3.5 Embedded reset and power control block characteristics Table 31. Reset and power control block characteristics (continued) 6.3.6 Embedded reference voltage characteristics Table 32. Embedded reference voltage Table 33. Internal reference voltage calibration values 6.3.7 Supply current characteristics Table 34. Typical and maximum current consumption in Run mode, code with data processing running from ITCM Table 35. Typical and maximum current consumption in Run mode, code with data processing running from AXISRAM3, cache ON Table 36. Typical and maximum current consumption in Run mode, code with data processing running from AXISRAM3, cache OFF Table 37. Typical and maximum current consumption in Run mode, code with data processing running from internal flash memory, cache ON Table 38. Typical and maximum current consumption in Run mode, code with data processing running from internal flash memory, cache OFF Table 39. Typical consumption in Run mode and corresponding performance versus code position Table 40. Typical and maximum current consumption in Sleep mode Table 41. Typical and maximum current consumption in System Stop mode Table 42. Typical and maximum current consumption in Standby mode Table 43. Typical and maximum current consumption in VBAT mode Table 44. Typical and maximum current consumption in Run mode, code with data processing running from Octo flash memory, cache OFF Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory, cache OFF Table 46. Typical and maximum current consumption: data write 50% toggle on 16-bit memory Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory Table 48. Typical and maximum current consumption: data write 12.5% toggle on 16-bit memory Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory Table 50. Typical dynamic current consumption of peripherals (continued) 6.3.8 Wake-up time from low-power modes Table 51. Low-power mode wakeup timings 6.3.9 External clock source characteristics Table 52. High-speed external user clock characteristics Figure 31. High-speed external clock source AC timing diagram Table 53. Timing for analog HSE input Figure 32. Analog HSE input waveform Table 54. Low-speed external user clock characteristics Figure 33. Low-speed external clock source AC timing diagram Table 55. Timing for analog LSE input Figure 34. Analog LSE input waveform Table 56. 4-50 MHz HSE oscillator characteristics Figure 35. Typical application with an 8 MHz crystal Table 57. Low-speed external user clock characteristics Figure 36. Typical application with a 32.768 kHz crystal 6.3.10 Internal clock source characteristics Table 58. HSI48 oscillator characteristics Table 59. HSI oscillator characteristics Table 60. CSI oscillator characteristics Table 61. LSI oscillator characteristics 6.3.11 PLL characteristics Table 62. PLL1 characteristics (wide VCO frequency range) Table 63. PLL1 characteristics (narrow VCO frequency range) 6.3.12 EMC characteristics Table 64. EMS characteristics Table 65. EMI characteristics for fHSE = 8 MHz and fCPU = 600 MHz 6.3.13 Absolute maximum ratings (electrical sensitivity) Table 66. ESD absolute maximum ratings Table 67. Electrical sensitivities 6.3.14 I/O current injection characteristics Table 68. I/O current injection susceptibility 6.3.15 I/O port characteristics Table 69. I/O static characteristics Figure 37. VIL/VIH for all I/Os except BOOT0 Table 70. Output voltage characteristics for all I/Os except PC13, PC14, and PC15 Table 71. Output voltage characteristics for PC13 Table 72. Output voltage characteristics for PC14 and PC15 Table 73. Output timing characteristics (HSLV OFF) (continued) Table 74. Output timing characteristics (HSLV ON) (continued) Table 75. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF) (continued) Table 76. Output timing characteristics VDDXSPIx 1.2 V (HSLV ON) (continued) 6.3.16 NRST pin characteristics Table 77. NRST pin characteristics Figure 38. Recommended NRST pin protection 6.3.17 FMC characteristics Table 78. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings Table 79. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings Figure 39. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms Table 80. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings Table 81. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings Figure 40. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms Table 82. Asynchronous multiplexed PSRAM/NOR read timings Table 83. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings Figure 41. Asynchronous multiplexed PSRAM/NOR read waveforms Table 84. Asynchronous multiplexed PSRAM/NOR write timings Table 85. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings Table 86. Synchronous non-multiplexed NOR/PSRAM read timings Figure 42. Synchronous non-multiplexed NOR/PSRAM read timings Table 87. Synchronous non-multiplexed PSRAM write timings Figure 43. Synchronous non-multiplexed PSRAM write timings Table 88. Synchronous multiplexed NOR/PSRAM read timings Figure 44. Synchronous multiplexed NOR/PSRAM read timings Table 89. Synchronous multiplexed PSRAM write timings Figure 45. Synchronous multiplexed PSRAM write timings Table 90. Switching characteristics for NAND flash read cycles Figure 46. NAND controller waveforms for read access Figure 47. NAND controller waveforms for common memory read access Table 91. Switching characteristics for NAND flash write cycles Figure 48. NAND controller waveforms for write access Figure 49. NAND controller waveforms for common memory write access Table 92. SDRAM read timings Table 93. LPSDR SDRAM read timings Figure 50. SDRAM read access waveforms (CL = 1) Table 94. SDRAM Write timings Table 95. LPSDR SDRAM Write timings Figure 51. SDRAM write access waveforms 6.3.18 XSPI interface characteristics Table 96. XSPI characteristics in SDR mode Table 97. XSPI characteristics in DTR mode (no DQS) Table 98. XSPI characteristics in DTR mode (with DQS)/Hyperbus Figure 52. XSPI DTR (with DQS) write timing diagram Figure 53. XSPI DTR (with DQS) read timing diagram Figure 54. XSPI DTR clock timing diagram 6.3.19 Delay block (DLYB) characteristics Table 99. Delay block characteristics 6.3.20 ADC characteristics Table 100. ADC characteristics (continued) Table 101. Minimum sampling time vs RAIN (12-bit ADC) (continued) Table 102. ADC accuracy 6.3.21 Voltage reference buffer characteristics Table 103. VREFBUF characteristics (continued) 6.3.22 Analog temperature sensor characteristics Table 104. Temperature sensor characteristics Table 105. Temperature sensor calibration values 6.3.23 Voltage booster for analog switch Table 106. Voltage booster for analog switch characteristics 6.3.24 Digital temperature sensor characteristics Table 107. Digital temperature sensor characteristics 6.3.25 VCORE monitoring characteristics Table 108. VCORE monitoring characteristics 6.3.26 Temperature and VBAT monitoring Table 109. VBAT monitoring characteristics Table 110. VBAT charging characteristics Table 111. Temperature monitoring characteristics 6.3.27 Audio digital filter (ADF) Table 112. ADF characteristics Figure 55. ADF timing diagram 6.3.28 Digital camera interface (DCMIPP) characteristics Table 113. DCMIPP characteristics Figure 56. DCMIPP timing diagram 6.3.29 Parallel synchronous slave interface (PSSI) characteristics Table 114. PSSI transmit characteristics Table 115. PSSI receive characteristics Figure 57. PSSI receive timing diagram Figure 58. PSSI transmit timing diagram 6.3.30 LCD-TFT controller (LTDC) characteristics Table 116. LTDC characteristics Figure 59. LCD-TFT horizontal timing diagram Figure 60. LCD-TFT vertical timing diagram 6.3.31 Timer characteristics Table 117. TIMx characteristics 6.3.32 Low-power timer characteristics Table 118. LPTIMx characteristics 6.3.33 Communication interfaces Table 119. I3C open-drain measured timing Table 120. I3C push-pull measured timing Table 121. I2C analog filter characteristics Table 122. USART characteristics Figure 61. USART timing diagram in master mode Figure 62. USART timing diagram in slave mode Table 123. SPI characteristics (continued) Figure 63. SPI timing diagram - slave mode and CPHA = 0 Figure 64. SPI timing diagram - slave mode and CPHA = 1 Figure 65. SPI timing diagram - master mode Table 124. I2S dynamic characteristics Figure 66. I2S slave timing diagram (Philips protocol)(1) Figure 67. I2S master timing diagram (Philips protocol)(1) Table 125. SAI characteristics Figure 68. SAI master timing waveforms Figure 69. SAI slave timing waveforms Table 126. MDIO slave timing parameters Figure 70. MDIO slave timing diagram Table 127. Dynamic characteristics: SD / MMC characteristics, VDD = 2.7 to 3.6 V Table 128. Dynamic characteristics: eMMC characteristics VDD = 1.71V to 1.9V Figure 71. SD high-speed mode Figure 72. SD default mode Figure 73. SDMMC DDR mode Table 129. USB OTG_FS electrical characteristics Table 130. USB OTG_HS DC electrical characteristics Table 131. OTG_HS current consumption characteristics Table 132. UCPD electrical characteristics Table 133. Dynamic characteristics: Ethernet MAC signals for SMI Figure 74. Ethernet SMI timing diagram Table 134. Dynamic characteristics: Ethernet MAC signals for RMII Figure 75. Ethernet RMII timing diagram Table 135. Dynamic characteristics: Ethernet MAC signals for MII Figure 76. Ethernet MII timing diagram Table 136. Dynamic JTAG characteristics Table 137. Dynamics SWD characteristics Figure 77. JTAG timing diagram Figure 78. SWD timing diagram 7 Package information 7.1 Device marking 7.2 VFQFPN68 package information (B029) Figure 79. VFQFPN68 - Outline Table 138. VFQFPN68 - Mechanical data Figure 80. VFQFPN68 - Recommended footprint 7.3 LQFP100 package information (1L) Figure 81. LQFP100 - Outline(15) Table 139. LQFP100 - Mechanical data Figure 82. LQFP100 - Recommended footprint 7.4 TFBGA100 package information (A08Q) Figure 83. TFBGA100 - Outline Table 140. TFBGA100 - Mechanical data Figure 84. TFBGA100 - Recommended footprint Table 141. TFBGA100 - Recommended PCB design rules (0.8 mm pitch BGA) 7.5 LQFP144 package information (1A) Figure 85. LQFP144 - Outline(15) Table 142. LQFP144 - Mechanical data Figure 86. LQFP144 - Recommended footprint 7.6 UFBGA144 package information (A02Y) Figure 87. UFBGA144 - Outline Table 143. UFBGA144 - Mechanical data (continued) Figure 88. UFBGA144 - Recommended footprint Table 144. UFBGA144 - Recommended PCB design rules (0.80 mm pitch BGA) 7.7 UFBGA169 package information (A0YV) Figure 89. UFBGA169 - Outline Table 145. UFBGA169 - Mechanical data (continued) Figure 90. UFBGA169 - Recommended footprint Table 146. UFBGA169 - Recommended PCB design rules (0.5 mm pitch BGA) 7.8 LQFP176 package information (1T) Figure 91. LQFP176 - Outline(15) Table 147. LQFP176 - Mechanical data Figure 92. LQFP176 - Recommended footprint 7.9 WLCSP101 package information (B0FA) Figure 93. WLCSP101L - Outline Table 148. WLCSP101 - Mechanical data Figure 94. WLCSP101 - recommended footprint Table 149. WLCSP101 - recommended PCB design rules 7.9.1 Device marking for WLCSP101 Figure 95. WLCSP101 marking example (package top view) 7.10 UFBGA(176+25) package information (A0E7) Figure 96. UFBGA(176+25) - Outline Table 150. UFBGA(176+25) - Mechanical data (continued) Figure 97. UFBGA(176+25) - Recommended footprint Table 151. UFBGA(176+25) - Recommended PCB design rules (0.65 mm pitch BGA) 7.11 TFBGA225 package information (B04V) Figure 98. TFBGA225 - Outline(13) Table 152. TFBGA225 - Mechanical data Figure 99. TFBGA225 - Recommended footprint Table 153. TFBGA225 - Recommended PCB design rules (0.8 mm pitch BGA) 7.12 Package thermal characteristics Table 154. Package thermal characteristics (continued) 8 Ordering information 9 Important security notice 10 Revision history Table 155. Document revision history