Datasheet MAX20480 (Analog Devices) - 10

MAX20480 Four- to Seven-Input Automotive Power-System Monitor Family
MAX20480D
TOP VIEW IN7P INM IN6P IN5 12 11 10 9 RESET 13 8 VDD ADDR 14 7 EN1 MAX20480 SDA 15 6 GND SCL 16 5 EN0 + 1 2 3 4 IN1 IN2 IN3 IN4 TQFN 3mm x 3mm
Pin Description PIN NAME FUNCTION MAX20480A MAX20480B MAX20480C MAX20480D
1 1 1 1 IN1 Input Voltage Monitor 1. 2 2 2 2 IN2 Input Voltage Monitor 2. 3 3 3 3 IN3 Input Voltage Monitor 3. 4 4 4 4 IN4 Input Voltage Monitor 4. Enable Input 0. Raise/lower the EN0 input to 5 5 5 5 EN0 indicate a transition from OFF→ON/ON→OFF, respectively, in the system. 6 6 6 6 GND Ground. Connect all grounds together at the EP. Enable Input 1. Raise/lower the EN1 input to 7 7 7 7 EN1 indicate a transition from SLEEP→ON/ ON→SLEEP, respectively, in the system. Input Supply Voltage. Connect a 0.1μF capacitor 8 8 8 8 VDD between VDD and GND and place close to the IC. 9 - - - GND Ground. Connect all grounds together at the EP. - 9 9 9 IN5 Input Voltage Monitor 5. 10 10 - - GND Ground. Connect all grounds together at the EP. - - 10 10 IN6P Differential Input Voltage Monitor 6. 11 11 - - GND Ground. Connect all grounds together at the EP. Common negative input for voltage monitors - - 11 11 INM IN6P and IN7P. 12 12 12 – GND Ground. Connect all grounds together at the EP. www.maximintegrated.com Maxim Integrated | 10 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 16-TQFN-EP Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Typical Operating Characteristics (continued) Pin Configurations MAX20480A MAX20480B MAX20480C MAX20480D Pin Description Pin Description (continued) Functional Diagram Detailed Description I2C Interface Bit Transfer STOP and START Conditions Early STOP Condition Clock Stretching I2C General Call Address Packet Error Checking (PEC) Slave Address Acknowledge Write-Data Format Read-Data Format Voltage Monitor DVS Operation DVS Command Sequence (Low to High): DVS Command Sequence (High to Low): I2C DVS Timing Example (Low to High) Flexible Power Sequence Recorder Windowed Watchdog and Reset Control Sample C Code For Challenge/Response Watchdog Window Settings RESET Output Enable Inputs (EN0/EN1) Comparator Power States Register Map Top Level Register Details ID (0x00) CONFIG1 (0x01) CONFIG2 (0x02) VMON (0x03) RSTMAP (0x4) STATOV (0x5) STATUV (0x6) STATOFF (0x7) VIN1 (0x8) VIN2 (0x9) VIN3 (0xA) VIN4 (0xB) VIN5 (0xC) VINO6 (0xD) VINU6 (0xE) VINO7 (0xF) VINU7 (0x10) OVUV1 (0x11) OVUV2 (0x12) OVUV3 (0x13) OVUV4 (0x14) OVUV5 (0x15) FPSSTAT1 (0x16) FPSCFG1 (0x17) UTIME1 (0x18) UTIME2 (0x19) UTIME3 (0x1A) UTIME4 (0x1B) UTIME5 (0x1C) UTIME6 (0x1D) UTIME7 (0x1E) DTIME1 (0x1F) DTIME2 (0x20) DTIME3 (0x21) DTIME4 (0x22) DTIME5 (0x23) DTIME6 (0x24) DTIME7 (0x25) WDSTAT (0x26) WDCDIV (0x27) WDCFG1 (0x28) WDCFG2 (0x29) WDKEY (0x2A) WDLOCK (0x2B) RSTCTRL (0x2C) CID (0x2D) Applications Information Diagnostics Typical Application Circuit Ordering Information Revision History