Datasheet LS7083N, LS7084N (LSI Computer Systems)

LSI/CSI
UL LS7083N
LS7084N ® LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 June 2015 QUADRATURE CLOCK CONVERTER VDD (Pin 2)
Supply Voltage positive terminal.
VSS (Pin 3)
Supply Voltage negative terminal.
A (Pin 4)
Quadrature Clock Input A. This input has a filter circuit to validate
input logic level and eliminate encoder dither.
B (Pin 5)
Quadrature Clock Input B. This input has a filter circuit identical
to input A.
Mode (Pin 6)
Mode is a 3-state input to select resolutions x1, x2 or x4. The selected resolution multiplies the input quadrature clock rate by 1, 2
and 4, respectively, in producing the outputs UPCK / DNCK and
CLK (see Figure 2).
The Mode input logic levels selects resolutions as follows:
Logic 0 = x1 Float = x2 Logic 1 = x4 7083N/84N-062315 -1 V DD (+V ) 2 V SS (-V ) 3 A 4 RBIAS 1 V DD (+V ) 2 V SS (-V ) 3 A 4 LS7084N INPUT/OUTPUT DESCRIPTION:
RBIAS (Pin 1)
Input for external component connection. A resistor connected
between this input and VSS adjusts the output clock pulse width
(Tow). For proper operation, the output clock pulse width must be
less than or equal to the A, B pulse separation (TOW ≤ TPS). 1 LSI DESCRIPTION:
The LS7083N and LS7084N are CMOS quadrature clock converters. Quadrature clocks derived from optical or magnetic encoders, when applied to the A and B inputs of the LS7083N or
LS7084N, are converted to strings of Up Clocks and Down
Clocks ( LS7083N) or to a Clock and an Up/Down direction control (LS7084N). These outputs can be interfaced directly with
standard Up/Down counters for direction and position sensing of
the encoder. RBIAS LS7083N Applications:
• Interface incremental encoders to Up / Down Counters
(See Figure 6A and Figure 6B)
• Interface rotary encoders to Digital Potentiometers
(See Figure 7) PIN ASSIGNMENT -TOP VIEW
LSI FEATURES:
• x1 and x4 mode selection
• Up to 16MHz output clock frequency
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +3V to +12V operation (VDD -VSS)
• LS7083N, LS7084N (DIP);
LS7083NS, LS7084NS (SOIC) -See Figure 1 8 UPCK 7 DNCK 6 MODE 5 B 8 CLK 7 UP/DN 6 MODE 5 B FIGURE 1 LS7083N -DNCK (Pin 7)
In LS7083N, this is the DOWN Clock Output. This output consists of
low-going pulses generated when A input lags the B input.
LS7084N -UP/DN (Pin 7)
In LS7084N, this is the count direction indication output. When A
input leads the B input, the UP/DN output goes high indicating that
the count direction is UP. When A input lags the B input, UP/DN
output goes low, indicating that the count direction is DOWN.
LS7083N -UPCK (Pin 8)
In LS7083N, this is the UP Clock output. This output consists of
low-going pulses generated when A input leads the B input.
LS7084N -CLK (Pin 8)
In LS7084N, this is the combined UP Clock and DOWN Clock output. The count direction at any instant is indicated by the UP/DN
output (Pin 7).
NOTE: For the LS7084N, the timing of CLK and UP/DN requires
that the counter interfacing with LS7084N counts on the rising edge
of the CLK pulses.