Datasheet TSB711, TSB711A TSB712, TSB712A (STMicroelectronics) - 4

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TSB711, TSB711A, TSB712, TSB712A Electrical characteristics 3 Electrical characteristics Table 5. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless otherwise specified) Symbol Parameter Conditions Min. Typ. Max. Unit DC performance
TSB711A, TSB712A, T = 25 °C, ±300 VCC- ≤ VICM ≤ VCC+ - 1.5 V TSB711A, TSB712A, T = 25 °C, VCC- ≤ VICM ≤ VCC+ ±650 TSB711A, TSB712A, -40 °C < T < 125 °C, ±580 VCC- ≤ VICM ≤ VCC+ - 1.5 V TSB711A, TSB712A, -40 °C < T < 125 °C, ±930 VCC- ≤ VICM ≤ VCC+ Vio Input offset voltage µV TSB711, TSB712, T = 25 °C, ±800 VCC- ≤ VICM ≤ VCC+ -1.5 V TSB711, TSB712, T = 25 °C, VCC- ≤ VICM ≤ VCC+ ±1200 TSB711, TSB712, -40 °C < T < 125 °C, ±1100 VCC- ≤ VICM ≤ VCC+ - 1.5 V TSB711, TSB712, -40 °C < T < 125 °C, ±1400 VCC- ≤ VICM ≤ VCC+ ΔVio / ΔT Input offset voltage drift -40°C < T < 125 °C (1) 2.8 µV/°C ΔV Long-term input offset voltage io drift T = 25 °C (2) 0.57 µV/√mo VICM = VCC+, T = 25 °C 0 300 VICM = VCC+, -40 °C < T < 125 °C 0 900 IIB Input bias current (3) VICM = VCC-, T = 25 °C -100 0 nA VICM = VCC-,-40 °C < T < 125 °C -200 0 VICM = VCC+ 10 IIO Input offset current (4) VICM = VCC- 10 RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V, 110 125 T = 25 °C AVD Open loop gain RL ≥ 10 kΩ, (VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) - 0.5 V, 105 -40 °C < T < 125 °C (VCC-) ≤ VICM ≤ ( VCC+) - 1.5 V, T = 25 °C 115 130 (VCC-) ≤ VICM ≤ (VCC+) - 1.5 V, -40 °C < T < 125 °C 110 TSB711A, TSB712A (VCC-) ≤ VICM ≤ (VCC+), dB 100 120 T = 25 °C Common-mode rejection ratio CMR TSB711A, TSB712A (V 20 log (∆V CC-) ≤ VICM ≤ (VCC+), INCM / ∆VIO) 95 -40 °C < T < 125 °C TSB711, TSB712 (VCC-) ≤ VICM ≤ (VCC+), T = 25 °C 90 120 TSB711 , TSB712 (VCC-) ≤ VICM ≤ (VCC+), 85 -40 °C < T < 125 °C
DS12487
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Rev 7 page 4/32
Document Outline TSB711, TSB711A, TSB712, TSB712A 1 Pin description 2 Absolute maximum ratings and operating conditions 3 Electrical characteristics 4 Typical performance characteristics 5 Application information 5.1 Operating voltages 5.2 Input pin voltage range 5.3 Rail-to-rail input stage 5.4 Input offset voltage drift over the temperature 5.5 Long term input offset voltage drift 5.6 EMI rejection 5.7 Maximum power dissipation 5.8 Capacitive load and stability 5.9 PCB layout recommendations 5.10 Decoupling capacitor 6 Typical applications 6.1 Low-side current sensing 7 Package information 7.1 SOT23-5 package information 7.2 MiniSO8 package information 7.3 SO8 package information 8 Ordering information Revision history