Datasheet ADP3051 (Analog Devices) - 10

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ADP3051 100% DUTY CYCLE OPERATION UNDERVOLTAGE LOCKOUT (UVLO)
The ADP3051 is capable of operating at 100% duty cycle, allow- The ADP3051 includes an internal undervoltage lockout ing it to regulate output voltages that are very close to the input (UVLO) circuit that turns off the converter if the input voltage. In 100% duty cycle operation, the P-channel switch voltage drops below the 2.2 V UVLO threshold. This prevents remains continuously on, and the dropout voltage is simply the uncontrolled behavior if the input voltage drops below the 2.7 V output current multiplied by the on resistance of the internal minimum allowable voltage range. The UVLO circuit includes switch and inductor, typically 200 mV at full loads (500 mA). 55mV of hysteresis to prevent oscillation at the UVLO
SHUTDOWN
threshold. The ADP3051 is enabled and disabled via its SHDN input.
SHORT-CIRCUIT PROTECTION AND RECOVERY
SHDN easily interfaces to open-drain and three-state logic When starting up or when the output is short circuited, the low GPIOs. To enable the ADP3051, drive SHDN to within 0.5 V of voltage drop across the synchronous rectifier may allow the the voltage at IN; to disable the ADP3051, drive SHDN below inductor current to run away because it rises more during the 0.4 V. The circuit of Figure 18 shows a simple means of driving on time than it falls during the off time. To protect against this, SHDN to the proper high and low input states in cases where no the ADP3051 automatically initiates a frequency foldback open-drain or three-state GPIO is available. operation when the voltage at FB drops below 0.3 V, allowing the ADP3051 to maintain control of the inductor current under these conditions.
IN
When operating at higher input voltages (for example, from a 5 V bus), the ADP3051 may exhibit output voltage overshoot
100k
Ω upon startup or after release of an overload condition (see Figure 9). In such cases, the ADP3051’s limited COMP slew rate
SHDN
can slow its recovery as the output approaches regulation, allowing the output voltage to overshoot. If overshoot cannot be tolerated in an application, the COMP voltage can be limited by
SHDN CONTROL
placing a Zener diode from COMP to GND, as shown in Figure 19.
ADP3051
04768-0-017
COMP 6
Figure 18. Shutdown Control Circuit
CMPZ4683-ADC ADP3051
04768-0-023 Figure 19. COMP Zener Clamp to Prevent Short-Circuit Recovery Output Voltage Overshoot Rev. 0 | Page 10 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIP TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM CONTROL MODE TRI-MODE OPERATION 100% DUTY CYCLE OPERATION SHUTDOWN UNDERVOLTAGE LOCKOUT (UVLO) SHORT-CIRCUIT PROTECTION AND RECOVERY APPLICATIONS RECOMMENDED COMPONENTS DESIGN PROCEDURE Setting the Output Voltage Inductor Selection OUTPUT CAPACITOR SELECTION Input Capacitor Selection Compensation Design CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE