Datasheet UDA1330ATS (NXP) - 8

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L3 INTERFACE
The fundamental timing of data transfers (see Fig.5) is essentially the same as the address mode. The maximum The following system and digital sound processing input clock frequency and data rate is 64f features can be controlled in the L3 mode of the s. UDA1330ATS: Data transfer can only be in one direction, consisting of • System clock frequency input to the UDA1330ATS to program sound processing and other functional features. All data transfers are by 8-bit • Data input format bytes. Data will be stored in the UDA1330ATS after • De-emphasis for 32, 44.1 and 48 kHz reception of a complete byte. • Volume A multibyte transfer is illustrated in Fig.6. • Soft mute.
Registers
The exchange of data and control information between the microcontroller and the UDA1330ATS is accomplished The sound processing and other feature values are stored through a serial interface comprising the following signals: in independent registers. The first selection of the registers • L3DATA is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 1 and bit 0 • L3MODE (see Table 5). • L3CLOCK.
Table 5
Selection of data transfer Information transfer through the microcontroller bus is organized in accordance with the L3 interface format, in
BIT 1 BIT 0 TRANSFER
which two different modes of operation can be 0 0 data (volume, de-emphasis, mute) distinguished: address mode and data transfer mode. 0 1 not used
Address mode
1 0 status (system clock frequency, data input format) The address mode (see Fig.4) is required to select a device communicating via the L3 interface and to define 1 1 not used the destination registers for the data transfer mode. Data bits 7 to 2 represent a 6-bit device address where The second selection is performed by the 2 MSBs of the bit 7 is the MSB. The address of the UDA1330ATS is data byte (bit 7 and bit 6). The other bits in the data byte 000101 (bit 7 to bit 2). If the UDA1330ATS receives a (bit 5 to bit 0) represent the value that is placed in the different address, it will deselect its microcontroller selected registers. interface logic. The ‘status’ settings are given in Table 6 and the ‘data’ settings are given in Table 7.
Data transfer mode
The selected address remains active during subsequent data transfers until the UDA1330ATS receives a new address command. 2001 Feb 02 8 Document Outline Features General Multiple format input interface DAC digital sound processing Advanced audio configuration Applications General description Ordering information Quick reference data Block diagram Pinning Functional description System clock Application modes Multiple format input interface Interpolation filter (DAC) Noise shaper Filter stream DAC Pin compatibility L3 interface Address mode Data transfer mode Registers Programming the features Limiting values Handling Thermal characteristics Quality specification DC characteristics AC characteristics Timing Application information Package outline Soldering Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods Data sheet status Disclaimers