Datasheet UDA1330ATS (NXP) - 5

link to page 5 link to page 5 link to page 7 link to page 5 NXP Semiconductors Product specification Low-cost stereo filter DAC UDA1330ATS
FUNCTIONAL DESCRIPTION
In the L3 mode, pin APPL0 must be set to LOW. It should be noted that when the L3 mode is used, an initialization
System clock
must be performed when the IC is powered-up. The UDA1330ATS operates in slave mode only. Therefore, in all applications the system devices must
Multiple format input interface
provide the system clock. The system frequency (fsys) is DATA FORMATS selectable and depends on the application mode. The options are: 256fs, 384fs and 512fs for the L3 mode and The digital interface of the UDA1330ATS supports multiple 256fs or 384fs for the static pin mode. The system clock format inputs (see Fig.3). must be locked in frequency to the digital interface input Left and right data-channel words are time multiplexed. signals. The WS signal must have a 50% duty factor for all The UDA1330ATS supports sampling frequencies from LSB-justified formats. 8 to 55 kHz. The BCK clock can be up to 64f
Application modes
s, or in other words the BCK frequency is 64 times the Word Select (WS) The application mode can be set with the three-level frequency or less: f ≤ BCK 64 × fWS. pin APPSEL (see Table 1):
Important
: the WS edge MUST fall on the negative edge • L3 mode of the BCK at all times for proper operation of the digital • Static pin mode with f interface. sys = 384fs • Static pin mode with fsys = 256fs. The UDA1330ATS also accepts double speed data for double speed data monitoring purposes
Table 1
Selecting application mode and system clock frequency via pin APPSEL L3 MODE
VOLTAGE ON
This mode supports the following input formats:
MODE f PIN APPSEL sys
• I2S-bus format with data word length of up to 20 bits VSSD L3 mode 256fs, 384fs or 512fs • MSB-justified format with data word length up to 20 bits 0.5VDDD 384fs • LSB-justified format with data word length of static pin mode VDDD 256fs 16, 18 or 20 bits. STATIC PIN MODE The function of an application input pin (active HIGH) depends on the application mode (see Table 2). This mode supports the following input formats: • I2S-bus format with data word length of up to 20 bits
Table 2
Functions of application input pins • LSB-justified format with data word length of
FUNCTION
16, 18 or 20 bits.
PIN L3 MODE STATIC PIN MODE
These four formats are selectable via the static pin codes SF0 and SF1 (see Table 3). APPL0 TEST MUTE APPL1 L3CLOCK DEEM
Table 3
Input format selection using SF0 and SF1 APPL2 L3MODE SF0
FORMAT SF0 SF1
APPL3 L3DATA SF1 I2S-bus 0 0 LSB-justified 16 bits 0 1 For example, in the static pin mode the output signal can be soft muted by setting pin APPL0 to HIGH. LSB-justified 18 bits 1 0 De-emphasis can be switched on for 44.1 kHz by setting LSB-justified 20 bits 1 1 pin APPL1 to HIGH; setting pin APPL1 to LOW will disable de-emphasis. 2001 Feb 02 5 Document Outline Features General Multiple format input interface DAC digital sound processing Advanced audio configuration Applications General description Ordering information Quick reference data Block diagram Pinning Functional description System clock Application modes Multiple format input interface Interpolation filter (DAC) Noise shaper Filter stream DAC Pin compatibility L3 interface Address mode Data transfer mode Registers Programming the features Limiting values Handling Thermal characteristics Quality specification DC characteristics AC characteristics Timing Application information Package outline Soldering Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods Data sheet status Disclaimers