Datasheet NDS331N (ON Semiconductor)

N-Channel Logic Level Enhancement Mode Field Effect Transistor NDS331N
General Description
These N−Channel logic level enhancement mode power field effect
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transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is D especially tailored to minimize on−state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMCIA cards, and other battery G S powered circuits where fast switching, and low in−line power loss are
SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9
needed in a very small outline surface mount package.
CASE 527AG Features
• 1.3 A, 20 V
MARKING DIAGRAM
♦ RDS(on) = 0.21 @ VGS = 2.7 V Drain ♦ RDS(on) = 0.16 @ VGS = 4.5 V 3 • Industry Standard Outline SOT−23 Surface Mount Package Using Proprietary SUPERSOTt−3 Design for Superior Thermal and 331M Electrical Capabilities 1 2 • High Density Cell Design for Extremely Low RDS(on) Gate Source • Exceptional On−Resistance and Maximum DC Current Capability M = Date Code • This is a Pb−Free Device D G S
ORDERING INFORMATION Device Package Shipping
† NDS331N SOT−23−3/ 3000 / SUPERSOT−23 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
May, 2021 − Rev. 7 NDS331N/D